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Description  |
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FIELD OF THE INVENTION
The present invention relates to a memory testing apparatus for testing a
memory in the form of an integrated circuit (a semiconductor integrated
circuit memory, hereinafter referred to as an IC memory), and
particularly, relates to a portion or section of such memory testing
apparatus including a failure analysis memory for storing test results of
an IC memory.
BACKGROUND OF THE RELATED ART
Storage capacity of an IC memory is increasing more and more, and
accordingly an increased IC chip area and formation of patterns at high
density are required. As a result, there is an increased possibility that
a lowering of the yield of IC memories caused by a very minute defect
occurs. In order to prevent the yield of IC memories from being lowered,
various failure relieving procedures or processes have been taken wherein
a failure or defect element is replaced by a substitute or alternative
element.
FIG. 12 generally shows an entire circuit arrangement of a prior
conventional memory testing apparatus, and FIG. 13 is an illustration of
the inside of an IC memory for explaining an analysis method for failure
relief. As shown in FIG. 13, an IC memory includes a main element 17 which
is a main storage portion, and four substitute elements 18, 19, 20 and 21
disposed around the main element 17 (in this example, at the lower side
and the right side of the main element). The main element 17 has, in this
example, the total of 64 storage elements in the form of a matrix of 8
rows.times.8 columns. As shown in the figure, rows are denoted by A, B, C,
. . . , H, respectively, and columns are denoted by a, b, c, . . . , h,
respectively, for brief explanation. Each of intersecting points or areas
Aa, Ab, Ac, . . . , Hh of rows and columns of the main element 17 forms a
unit element which is a unit storage element of the IC memory.
The substitute elements 18, 19, 20 and 21 are previously provided in the IC
chip for a failure relief and each substitute element comprises a
plurality of unit storage elements. In this example, four substitute
elements are shown. However, the number of substitute elements and the
disposed locations in the IC chip may be arbitrarily selected as the case
may be.
Assuming that the IC memory shown in FIG. 13 was tested by a memory testing
apparatus shown in FIG. 14 to be described later, and as a result,
failures or defects were found in, for example, four unit elements Bb, Be,
Df and Fe as shown in FIG. 13 by oblique lines, the row B including the
failure unit elements Bb and Be, the column f including the failure unit
element Df, and the row F including the failure unit element Fe are
removed from the main element 17 so that no failure unit element exists in
the main element 17.
Then, the substitute element 18 is substituted for the row B, the
substitute element 19 is substituted for the row F, and the substitute
element 20 is substituted for the column f. In such a way, by replacing a
row or rows and/or a column or columns each including one or more failure
unit elements by such substitute elements, the IC memory can be relieved
such that all of the addresses thereof can be used even if the IC memory
has one or more failure unit elements in the main element 17 thereof.
As described above, in order to relieve an IC memory of a failure element
or elements, "information for indicating at which address or addresses a
failure unit element or elements exist" which is called a failure map is
necessary, and hence, as shown in FIG. 12, a memory testing apparatus
having a failure analysis memory (failure memory) 16 for storing therein
failure information (data) is used.
This memory testing apparatus comprises a timing generator (TMG GEN) 22, a
pattern generator (PTN GEN) 23 and a waveform shaping device (WAVE SHAPE)
24 whereby a predetermined test pattern signal is generated and is applied
to a memory under test (IC memory under test) MUT to write predetermined
data in the memory under test MUT (hereinafter referred to as MUT). The
data written in the MUT are read out therefrom later to supply to a
logical comparator (LG COMPA) 14 as a response output signal.
The pattern generator 23 supplies a test pattern signal to an MUT via the
waveform shaping device 24 and also supplies an expected value pattern
signal (EXP SIG) directly to the logical comparator 14. Further, the
pattern generator 23 supplies an address signal (ADR SIG) to the failure
analysis memory (FAIL MEM) 16, the address signal specifying the same
address as that of an address signal added to both the test pattern signal
and the expected value pattern signal.
The logical comparator 14 compares a response output signal read out from
an MUT with an expected value pattern signal outputted from the pattern
generator 23 and detects as to whether there is an anti-coincidence or
mismatch between both signals. That is, when the response output signal
does not coincide with the expected value pattern signal, the logical
comparator 14 writes in the failure analysis memory 16 a failure signal or
data (FAIL SIG) indicating a location of a failure cell (unit element) in
the main element 17 of the MUT. The address of the failure analysis memory
16 into which the failure data is written is the same address as the MUT
address at which the anti-coincidence has occurred, and the address signal
specifying that MUT address is supplied directly to the failure analysis
memory 16 from the pattern generator 23, as mentioned above.
The failure analysis memory 16 is provided with a memory having at least
the same storage capacity as that of the MUT and the memory is initialized
before starting a test. For example, the memory of the failure analysis
memory 16 is initialized by writing logical "0s" in all of the addresses
thereof. When a failure signal is generated from the logical comparator 14
during a test of an MUT, a mark is written in an address in the memory of
the failure analysis memory 16 specified by the above address signal. That
is, for example, a logical "1" is written in that address.
In such a way, failure address information of an MUT specifying the
addresses of the MUT associated with the failures which occurred during a
series of tests is stored in the failure analysis memory 16. The failure
data stored in the failure analysis memory 16 are read out therefrom after
all of the tests for an MUT are completed. When such failure data are
utilized for relieving an MUT of its failure memory element for instance,
a failure map is created, which is read out into an arithmetic and logic
(hereinafter referred to as arithmetic) or computing part (ALU) 15 to
determine a row or rows and/or a column or columns to be relieved.
On the other hand, in a usually utilized testing method such as a marching
method or a galloping method or the like, since a plurality of reading
tests are performed on the same address of an MUT in a series of tests, a
plurality of failure signals may be generated with respect to the same
address signal. However, regarding the failure of the same address, a
plurality of marks are repeatedly written in the same address one over
another so that only information required for the failure relief can be
stored.
As described above, the failure analysis memory 16 has at least the same
storage capacity as that of an MUT. Whenever a failure signal is
generated, a logical "1" is written in the same address location of the
failure analysis memory 16 as that of the unit element which has generated
the failure signal. Therefore, the failure analysis memory 16 must have at
least the same storage capacity as that of an MUT as well as operate at
the same operating rate or speed as that of the MUT. For that reason, a
conventional failure analysis memory has been constructed by using memory
elements called static RAM (SRAM) which can operate at high operating
rate. However, since an SRAM is expensive and in addition, an SRAM having
large storage capacity cannot be produced, there is a problem that a
failure analysis memory having a large storage capacity must be
constituted by using a large number of SRAMs.
Consequently, an attempt for using a dynamic RAM (DRAM) which operates at
low operating rate or speed, but is inexpensive has been made to construct
a failure analysis memory. FIG. 14 shows a circuit construction of a
failure analysis memory contemplated in case a DRAM is used.
A method can be contemplated wherein a switching circuit MP and a plurality
of memory banks BK#1, BK#2, BK#3, . . . , BK#N are provided in a failure
analysis memory 16, and each time a failure signal (failure data) is
generated, the switching circuit MP switches the memory banks BK#1-BK#N
from one memory bank to next succeeding memory bank to supply the failure
signal to the one memory bank thereby distributing the failure data into
the plurality of memory banks BK#1, BK#2, BK#3, . . . , BK#N in regular
sequence to store therein. This method is generally called an interleave
method. By employing this interleave structure, the memory banks BK#1-BK#N
can be used each of which operates at an operating rate or speed which is
1/N of that of an MUT.
In case the interleave structure shown in FIG. 14 is employed, an address
signal having an address at which a failure signal is generated and the
failure signal are randomly supplied to each of the memory banks
BK#1-BK#N, and therefore, each of the memory banks BK#1-BK#N requires the
same memory capacity as that of an MUT. As a result, when an interleave
structure of N phases is arranged, each memory bank must have the memory
capacity of N times larger than that of an MUT. Accordingly, there is a
shortcoming that the amount of usage of memory elements is increased in
proportion to the number of phases N of interleave structure.
In addition, when a failure map which is the information necessary for a
relief operation is read out of the failure analysis memory 16 to the
computing part 15, in order to obtain the information required to
determine whether a relief is necessary or not, the data the number of
which is equal to that of all of unit elements constituting an MUT must be
read out of the failure analysis memory 16. A long time is necessary for
this operation. Consequently, there is a disadvantage that it takes a long
time to determine whether a relief is necessary or not, resulting in worse
in operation or work efficiency.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a memory testing
apparatus which can reduce the amount of information read out of a failure
analysis memory to an arithmetic part for a failure relief, thereby to be
able to significantly reduce the time duration required to determine
whether a relief is necessary or not.
It is a second object of the present invention to provide a memory testing
apparatus which can reduce the memory capacity of each memory bank in case
a failure analysis memory is constructed using an interleave structure.
It is a third object of the present invention to provide a memory testing
apparatus which can prevent, when failure signals are generated from the
same address in the close test cycles, the second failure signal and the
failure signal or signals subsequent thereto generated from the same
address from being written in a failure analysis memory, whereby the
writing frequency of failure signals into the failure analysis memory can
be reduced and hence each memory bank is not necessary to operate at a
high operating rate.
According to a first aspect of the present invention, a memory testing
apparatus is provided, wherein the amount of information read out to the
arithmetic part for the relief of a failure is reduced and the time for
determining whether a relief is necessary or not is significantly reduced
by using a failure cell array comprising a plurality of failure cells
connected in cascade for storing addresses of only failure unit elements
as a result of tests, instead of a conventional failure analysis memory
for storing the test result, i.e., presence or absence of a failure, for
each of all of the unit elements constituting an MUT.
According to a second aspect of the present invention, there is provided a
memory testing apparatus arranged such that when a failure analysis memory
is constructed in the form of an interleave structure, a switching circuit
for distributing failure data into memory banks is controlled to be
switched depending upon an address at which a failure has occurred.
That is, the switching circuit is controlled to be switched in accordance
with a value of the least significant bit or bits of the address at which
a failure has occurred and hence the failure occurrence addresses to be
stored in the respective memory banks are classified in accordance with
the value of the least significant bit or bits of the address.
Therefore, by employing the arrangement according to the second aspect of
the present invention, assuming that, for example, the switching circuit
is controlled in accordance with a value of the least significant two bits
of the address at which a failure has occurred, the total addresses to be
written in respective memory banks are classified 1/4 by 1/4 and
distributed into each memory bank by 1/4 of the total addresses.
Therefore, the storage capacity of each memory bank can be limited to 1/4
of that of an MUT.
According to a third aspect of the present invention, a problem caused by
use of the construction according to the second aspect can also be
eliminated.
That is, when a switching operation of the switching circuit is controlled
in accordance with a value of the least significant bit or bits as
described above, if the same address is accessed in close test cycles and
a failure occurs at the same address in each test cycle, the failure data
must be written continuously in the same memory bank.
Such situation occurs when a test by an inter-cell interference test
pattern is performed. The inter-cell interference test pattern includes,
for example, a galloping pattern, a ping-pong pattern, a butterfly
pattern, etc., and is a test pattern for alternately performing, for
instance, a reading operation out of and a writing operation in a memory
cell of interest and memory cells which are considered to interfere with
the interested memory cell as a center thereof and checking whether the
content of the interested memory cell is broken or not.
When a test by the inter-cell interference test pattern is performed, if a
memory cell of interest is a failure cell, a failure occurs at the same
address in each of the close test cycles. Therefore, in case a memory bank
for storing failure data is specified in correspondence with a value of
the least significant bit or bits of an address at which a failure has
occurred, if failures continuously occur at the same address, a situation
would occur where failure data have to be continuously written in the same
memory bank. As a result, that memory bank would be required to operate at
a high operating rate.
In order to eliminate this problem, according to the third aspect of the
present invention, there is provided means for inhibiting, when failures
occur at the same address in close test cycles, failure data of the second
occurrence and of the subsequent occurrence or occurrences generated at
the same address from being written. By this means for inhibiting, the
writing frequency of failure data in a memory bank can be reduced, and
thus a memory bank is not required to operate at a high operating rate.
Therefore, according to the second and the third aspects of the present
invention, there are obtained an advantage that a failure analysis memory
can be constructed by reduced numbers of memory elements each of which is
required to operate at a high operating rate, and an advantage that a low
cost memory element can be used.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a specific example of a failure cell used
in a memory testing apparatus according to the present invention;
FIG. 2 is a block diagram showing a specific example of a failure cell
array used in a memory testing apparatus according to the present
invention;
FIG. 3 is a block diagram generally showing an entire construction of a
first embodiment of the memory testing apparatus according to the present
invention;
FIG. 4 is a block diagram showing an entire construction of a specific
example of a failure analysis memory used in a second embodiment of the
memory testing apparatus according to the present invention;
FIG. 5 is a block diagram showing a specific example of a pipeline register
of a failure analysis memory used in the memory testing apparatus
according to the present invention;
FIG. 6 is a diagram for explaining the operation of the second embodiment
of the memory testing apparatus according to the present invention;
FIG. 7 is a diagram for explaining the operation of the second embodiment
of the memory testing apparatus according to the present invention;
FIG. 8 is a diagram for explaining the operation of the second embodiment
of the memory testing apparatus according to the present invention;
FIG. 9 is a diagram for explaining the operation of the second embodiment
of the memory testing apparatus according to the present invention;
FIG. 10 is a diagram for explaining an example of a test pattern for
testing an IC memory;
FIG. 11 is a diagram for explaining an example of an inter-cell
interference test pattern used in testing an IC memory;
FIG. 12 is a block diagram generally showing an entire construction of an
example of a conventional memory testing apparatus;
FIG. 13 is an illustration for explaining an example of a failure relieving
method in which an internal structure of an IC memory provided with
substitute elements is illustrated; and
FIG. 14 is a block diagram showing a specific example of a failure analysis
memory in which a DRAM is used.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First, a first embodiment of the memory testing apparatus according to the
present invention will be explained with reference to FIG. 3. Further, in
order to simplify the explanation, portions or elements in FIG. 3
corresponding to those in FIG. 12 have the same reference characters
affixed thereto as those in FIG. 12 and the explanation thereof will be
omitted unless it is necessary.
The memory testing apparatus shown in FIG. 3 is a memory testing apparatus
where a failure cell array (FAIL CELL ARRAY) 2 is used instead of the
failure analysis memory 16 in the conventional memory testing apparatus
shown in FIG. 12. The memory testing apparatus shown in FIG. 3 is the same
as the conventional memory testing apparatus except this point. The
failure cell array 2 receives, similarly to the failure analysis memory
16, a failure signal (FAIL SIG) outputted from the logical comparator (LG
COMPA) 14, an address signal (ADR SIG) supplied from the pattern generator
(PTN GEN) 23 for acquiring the failure signal, a clock signal (CLK SIG)
supplied from the timing generator (TMG GEN) 2 and a reset signal (not
shown) from a system bus. The failure cell array 2 which has received
those signals stores information for creating a failure map as will be
explained below, and outputs the information to the arithmetic or
computing part (ALU) 15 as information needed for determining whether a
relief is necessary or not.
Next, a specific example of the failure cell array 2 will be explained in
detail with reference to FIG. 2.
The failure cell array 2 is constituted by a plurality of failure cells 1
and each failure cell 1 has a terminal AIN for receiving from the pattern
generator an address signal for acquiring a failure signal, a terminal
AOUT for sending out the address signal, a terminal FIN for receiving the
failure signal, a terminal FOUT for sending out the failure signal, a
terminal CKIN for receiving a clock signal and a terminal RIN for
receiving a reset signal.
The first failure cell 1 depicted at the leftmost position in the figure
among the plurality of failure cells 1 receives at the terminal AIN an
address signal from the pattern generator 23 and receives at the terminal
FIN a failure signal from the logical comparator 14.
The second failure cell 1 receives at the terminal AIN an output signal
from the terminal AOUT of the first failure cell 1 and receives at the
terminal FIN an output signal from the terminal FOUT of the first failure
cell 1.
Similarly, each failure cell 1 among the third failure cell, the fourth
failure cell, . . . , receives at its terminals AIN and FIN output signals
from the terminals AOUT and FOUT of the failure cell 1 of the previous
stage, respectively. Also, the terminals CKIN and the terminals RIN of all
the failure cells 1 are connected in parallel, respectively.
In such a way, the plurality of failure cells 1 constructing the failure
cell array 2 are connected in cascade such that the terminals AIN and AOUT
are interconnected and the terminals FIN and FOUT are interconnected to
construct the failure cell array 2 which sequentially transfers an address
signal for acquiring a failure signal and a failure signal. Further, each
of all the failure cells 1 receives at the terminal RIN a reset signal at
the test starting time and the status is initialized to initial status
where any failure information is not held in the failure cell 1.
During a test, when the first failure element is detected in an MUT, an
address signal from the pattern generator 23 and a failure signal from the
logical comparator 14 are supplied to the terminals AIN and FIN of the
first failure cell 1 respectively. At this time, the first failure cell 1
is in the initial status in which any failure information is not held
therein. Therefore, when the address signal and the failure signal are
supplied to the first failure cell 1, the failure information is just held
therein and only the status is changed to holding status in which failure
information is held therein. Thus failure information is not sent to the
terminal FOUT.
At a later time during the test, when the second failure element is
detected in the MUT and an address signal and a failure signal are
supplied to the first failure cell 1, since the first failure cell 1 is
already in holding status in which failure information is held therein,
the address signal currently being received at the terminal AIN is
compared with the address of the failure information held in the first
failure cell 1. When both addresses are identical, a failure signal is not
sent to the terminal FOUT. When both addresses are not identical, a
failure signal is sent to the terminal FOUT and an address signal is sent
to the terminal AOUT.
Accordingly, when the first failure cell 1 does not send out a failure
signal to the terminal FOUT thereof, there is no status change in the
second failure cell 1 and the subsequent failure cells 1. However, when
the first failure cell 1 sends out a failure signal to the terminal FOUT
thereof, the second failure cell 1 receives an address signal and a
failure signal at the terminals AIN and FIN thereof, respectively.
When the second failure signal is supplied from the first failure cell 1 to
the second failure cell 1, like the case in which the first failure signal
is supplied to the first failure cell 1, the second failure cell 1 holds
the failure information therein and changes its status to a holding status
since the second failure cell 1 is in the initial status. Consequently, a
failure signal is not sent out to the terminal FOUT of the second failure
cell 1.
After that, when the third failure element is detected in the MUT, each of
the first and the second failure cells 1 compares the address of the
failure information held therein with the address signal currently being
received at the terminal AIN thereof. When both addresses are identical, a
failure signal is not sent to the terminal FOUT. However, when both
addresses are not identical, a failure signal is sent to the terminal FOUT
and an address signal is sent to the terminal AOUT.
In such a way, each time a failure element is detected in an MUT, each
failure cell 1 determines as to whether or not a failure signal should be
sent to the terminal FOUT. An address signal which is different from an
address of failure information held in any of the failure cells 1 is
transferred together with a failure signal in regular sequence to the
failure cells 1 at the subsequent stages. The address signal is held in a
failure cell 1 which is in the initial status among the subsequent failure
cells, and is stored in the failure cell array 2 as information for
creating a failure map of the MUT to be read out to the computing part 15
for determining whether to relieve or not.
Next, a specific example of a failure cell 1 will be described in detail
with reference to FIG. 1.
A failure cell 1 comprises an address hold register 3, an address transfer
register 4, an address comparator 5, a status hold register 6, a status
transfer register 7, and a controller 8.
The address hold register 3 is constructed by an n bit synchronous type
latch of D type. The address hold register 3 acquires, in synchronization
with a clock signal received at the terminal CKIN of the failure cell 1,
an address signal for taking a failure signal in the failure cell received
at the terminal AIN of the failure cell 1 when a latch enable signal from
the controller 8 is logical 1. Then the address signal is sent to the
address comparator 5.
The address transfer register 4 is made up of an n bit D type flip flop
(referred to as FF hereinafter). The address transfer register 4 acquires,
in synchronization with a clock signal received at the terminal CKIN of
the failure cell 1, an address signal for failure signal acquisition
received at the terminal AIN of the failure cell 1 and sends it out to the
terminal AOUT of the failure cell 1 as an address signal for taking a
failure in for the next stage.
The address comparator 5 is made up of an n bit digital comparator. The
address comparator 5 receives an address signal for failure signal
acquisition received at the terminal AIN of the failure cell 1 and an
output signal of the address hold register 3 and sends a signal of logical
1 to the controller 8 when each corresponding bit matches each other
between the both signals.
The status hold register 6 is made up of a JK type FF. The status hold
register 6 receives at J terminal a failure signal received at the
terminal FIN of the failure cell 1 and receives at CK terminal a clock
signal received at the terminal CKIN of the failure cell 1. K terminal of
the status hold register 6 is always fixed to a logical 0. The status hold
register 6 sends a status signal of the failure cell 1 to the controller
8.
The status transfer register 7 is made up of a D type FF. The status
transfer register 7 receives at D terminal a failure signal for the next
stage from the controller 8 and receives at CK terminal a clock signal
received at the terminal CKIN of the failure cell 1, and further, sends a
failure signal for the next stage to the terminal FOUT of the failure cell
1.
The controller 8 includes an AND gate 8 and receives a failure signal
received at the terminal FIN of the failure cell 1 and a status signal
from the status hold register 6. Then the controller 8 sends a latch
enable signal to the address hold register 3 and sends a failure signal
for the next stage to the status transfer register 7. A reset signal
received at the terminal RIN of the failure cell 1 is sent to respective R
terminals of the address hold register 3, the address transfer register 4,
the status hold register 6 and the status transfer register 7.
The failure cell 1 arranged as described above operates as follows.
1. The address hold register 3, the address transfer register 4, the status
hold register 6 and the status transfer register 7 are initialized to
initial status of logical 0 . The address transfer register 4 sends, in
synchronization with a clock signal, an address signal for taking a
failure in to the terminal AOUT as an address signal for taking a failure
in for the next stage.
2. Upon receipt of a failure signal when the status hold register 6 is in
initial status of logical 0 , the status hold register 6 is changed to
holding status of logical 1 in synchronization with a clock signal. At the
same time, an AND gate 8A outputs a logical 1 and the address hold
register 3 is enabled. Then, an address signal for taking a failure in is
taken in the address hold register 3 in synchronization with a clock
signal. On the other hand, since the AND gate 8B receives a logical 0
signal from the status hold register 6, the AND gate 8B outputs a logical
0 . Since the D terminal of the status transfer register 7 to which the
output of the AND gate 8B is applied is logical 0 , the status transfer
register 7 remains logical 0 even if it receives a clock signal at the CK
terminal. Thus, a failure signal for the next stage is not sent out to the
terminal FOUT of the failure cell 1.
3. Upon receipt of a failure signal when the status hold register 6 is in
holding status of logical 1 , the AND gate 8A in the controller 8 outputs
logical 0 , and thus the address hold register 3 is not enabled and
remains unchanged even if it receives a clock signal at the CK terminal.
On the other hand, the AND gate 8B receives an output signal of | | |
