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BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to the testing of integrated circuits, and
more specifically relates to a method for testing interconnections between
integrated circuits in a manner that avoids signal contention.
2. Background Art
The proliferation of modern electronics into our everyday life is due in
large part to the existence, functionality and relatively low cost of
advanced integrated circuits. As technology moves ahead, the
sophistication of electronic systems increases. An important aspect of
manufacturing an advanced electronic system is the ability to thoroughly
test the components and subassemblies in the system. Many semiconductor
manufacturers have provided various built-in self-test circuits on-chip to
help to test the functionality of individual integrated circuits located
on the chip. The testability of semiconductors was enhanced with the
development of boundary-scan testing, as disclosed in IEEE Standard 1149.1
"Standard Test Access Port and Boundary Scan Architecture." Boundary scan
testing allows an integrated circuit to be tested by placing shift
registers between functional circuitry and input/output pins when the
device is placed in test mode. Test data is typically serially scanned
into the shift registers to drive certain inputs, clocks are applied,
results are captured, and the resultant outputs are determined by shifting
the data out of the registers. The serial shift register elements that
make up the boundary scan circuitry is known as a scan chain, because test
data may be shifted or "scanned" into or out of the daisy-chained boundary
scan registers.
In addition to testing the circuitry on a particular integrated circuit,
more recent efforts have also recognized the need to test the
interconnections between integrated circuits on an electronic assembly.
Testing an electronic assembly, such as a printed wiring board or a system
that contains multiple printed wiring boards, is difficult using
traditional testing techniques. With the increasing popularity of surface
mount technology, feature sizes of printed wiring boards have decreased
significantly, making it increasingly difficult for automatic test
equipment to contact device pins. In addition, multi-chip module
technology is gaining widespread acceptance. Many connections within an
multi-chip module are not available for contact to an external tester. For
these, and many other reasons, testing of electronic assemblies by use of
the IEEE 1149.1 boundary scan standard has become very popular. The 1149.1
standard provides a standardized methodology for applying test patterns
without the need for a test fixture to contact the functional pins of
integrated circuits mounted on the printed wiring board.
Interconnections on an electronic assembly may be tested using boundary
scan testing by shifting in appropriate test data into the scan chain, by
pulsing one or more clocks to apply the test pattern and capture data, and
by shifting the results data out of the boundary scan chain. In a typical
electronic assembly, more than one integrated circuit may be able to drive
a given net. Lets assume that two integrated circuits may drive the same
net. The test vectors will be constructed and checked in a way that
assures that no test vector will cause both drivers to drive the nets to
opposite states at the same time. However, skew in signal lines and
propagation delays may result in short-term contention when making the
transition between test patterns. For example, if one integrated circuit
drives a net high during one test vector, and a different integrated
circuit drives the same net low during the following test vector, it is
possible that both drivers will be driving the net for a short time during
the transition. This possibility becomes more pronounced when
interconnected integrated circuits are on different scan chains that must
work together to test the interconnections.
Very short periods of contention would probably not significantly reduce
the life of an integrated circuit. Thus, if interconnect testing were
performed as a one-time manufacturing test, this contention problem would
probably not warrant any great concern. However, more and more systems are
performing interconnect testing as part of a built-in self-test procedure
each time the system is powered up or reset. Subjecting the integrated
circuits to repeated contention may significantly reduce the lifetimes of
the integrated circuits. Without a method for avoiding contention during
boundary scan testing, the life of the tested integrated circuits will be
cut short.
DISCLOSURE OF INVENTION
According to the present invention, methods for testing interconnections on
an electronic assembly in accordance with the disclosed embodiments
eliminate some or all signal line contention during boundary scan testing.
Each of these methods assumes that a first sequence of test patterns for
testing the interconnects has been generated. A method in accordance with
the first embodiment determines a safe pattern, and inserts the safe
pattern between every two patterns in the first sequence of test patterns
to generate a second sequence of test patterns. A method in accordance
with the second embodiment analyzes the first sequence of test patterns,
determines when a transition between two test patterns may cause possible
signal contention, and inserts a safe test pattern between the two to
generate a second sequence of test patterns. When a transition between two
test patterns may potentially cause contention, the transition is said to
be unsafe. The safe test pattern in the second embodiment may be a single
safe test pattern for all transitions, or may be a safe test pattern that
is derived from the two test patterns that generate the unsafe transition.
A method in accordance with the third embodiment analyzes the first
sequence of test patterns, reorders the test patterns to minimize the
number of unsafe transitions, and then inserts a safe test pattern between
patterns at unsafe transitions, if any, to assure that no signal
contention occurs during boundary scan testing. The safe test pattern for
the third embodiment may be a single test pattern, or may be a test
pattern that is derived from the test patterns that generate the unsafe
transition.
The foregoing and other features and advantages of the invention will be
apparent from the following more particular description of preferred
embodiments of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
The preferred embodiments of the present invention will hereinafter be
described in conjunction with the appended drawings, where like
designations denote like elements, and:
FIG. 1 is a block diagram of an on-chip test configuration that supports
interconnect testing;
FIG. 2 is a block diagram of one of the boundary scan cells shown in FIG.
1;
FIG. 3 is a block diagram showing how the test access ports of three
integrated circuits may be daisy chained together to form a boundary scan
chain;
FIG. 4 is a schematic view of an example electronic assembly that contains
three integrated circuits and two different boundary scan chains;
FIG. 5 is a flow diagram of a method in accordance with a first embodiment
of the present invention for assuring that no contention will occur during
boundary scan testing;
FIG. 6 is a flow diagram of a method in accordance with a second embodiment
of the present invention for assuring that no contention will occur during
boundary scan testing;
FIG. 7 is a flow diagram of a method for determining whether a transition
from one pattern A to another pattern B is safe;
FIG. 8 is a flow diagram of a method for generating a safe pattern I
between two test patterns A and B;
FIG. 9 is a flow diagram of a method in accordance with a third embodiment
of the present invention for assuring that no contention will occur during
boundary scan testing;
FIG. 10 is a flow diagram of a method for reordering test patterns in
accordance with the third embodiment;
FIG. 11 is a flow diagram of a method for constructing a safe transition
graph in accordance with the third embodiment;
FIG. 12 is a schematic diagram of an example electronic assembly that has
three interconnected integrated circuits;
FIG. 13 is a table of a first sequence of test patterns for the circuit of
FIG. 12;
FIG. 14 is a table showing the data and driver transitions for the test
patterns of FIG. 13; and
FIG. 15 is a safe transition graph for the circuit and test patterns of
FIGS. 12-14.
BEST MODE FOR CARRYING OUT THE INVENTION
Overview
Understanding the present invention requires a basic knowledge of boundary
scan testing techniques, discussed below. Those who are familiar with the
concepts relating to boundary scan testing may prefer to proceed with the
Detailed Description section.
Boundary Scan Testing
As discussed in the Background section, boundary-scan testing, as disclosed
in IEEE Standard 1149.1, allows an integrated circuit to be tested by
placing shift registers between functional circuitry and input/output pins
when the device is placed in test mode. Referring to FIG. 1, an integrated
circuit 100 that has boundary scan circuitry includes operational
circuitry 170, a plurality of input/output pins such as 105-125, a test
access port 101, and a plurality of boundary scan cells 130. Operational
circuitry 170 is the circuitry that is active during normal operation of
device 100. In a normal mode of operation, operational circuitry 170 is
coupled to input/output pins 110-125. Only in test or sample mode do
boundary scan cells 130 become active.
The serial chain of boundary scan cells 130 is known as a scan chain 160,
because test data may be shifted or "scanned" into or out of the
daisy-chained boundary scan registers 130. Some input/output pins such as
105-107 provide needed control inputs into the circuitry of scan chain
160, such as shift clock signals to load and empty the scan chain. In the
1149.1 standard, an on-chip controller known as a test access port
controller 101 provides the control signals to the boundary scan
registers. In test mode, boundary scan cells 130 interrupt the signals to
and from operational circuitry 170 that normally pass through to
input/output pins 110-125. Boundary scan cells 130 typically include shift
registers that allow test data to be shifted into the test data in input
(pin 108), and that allow test results to be shifted out on the test data
out output (pin 109). Test data is typically serially scanned into the
test data in input (pin 108) of scan chain 160 to cause certain boundary
scan cells to drive their respective pins. Clocks are then applied,
results are captured, and the results are determined by shifting the data
out of scan chain 160 at the test data out output (pin 109).
Referring to FIG. 2, one configuration for a suitable boundary scan cell
130 includes latches 210, 212, 220, 222 and 224; muxes 250, 260 and 270;
output driver 230, and input buffer 240. The concepts of the present
invention apply to any boundary scan cell configuration that supports the
method steps outlined herein. Latches 210, 212, 220, 222 and 224 contain
test data that is shifted into device 100 via a Scan Data In input, which
is coupled to the test data in input (pin 108). A clock signal
Shift/Capture Clock is provided to shift data present at the scan data in
SDI input into latches 210, 220 and 224 and to capture data present on the
input/output to latch 224. A second clock signal Update Clock is provided
to latch data present on the outputs of latches 210 and 220 into latches
212 and 222. The Shift/Capture Clock and Update Clock are suitably derived
from the IEEE 1149.1 standard test clock signal TCK. The operation of cell
130 is well-known in the art, and is not discussed in further detail
herein. Note that many other types of boundary scan cells may be used in
accordance with the method of the present invention.
Boundary Scan Testing of Interconnects
The boundary scan methodology of testing interconnections in an electronic
assembly has gained great importance in recent years. Referring to FIG. 3,
a sample electronic assembly 300 includes integrated circuits 310, 320 and
330. Integrated circuit 310 includes internal logic 312 and a boundary
scan circuit 314 that includes a test access port 316. In similar fashion,
integrated circuits 320 and 330 include corresponding internal logic 322
and 332, boundary scan circuits 324 and 334, and test access ports 326 and
336. Each integrated circuit 310, 320 and 330 are interconnected via
functional interconnects 340. The goal of interconnect testing via
boundary scan techniques is to assure that all functional interconnections
340 between integrated circuits are correct.
A scan chain is formed by daisy-chaining the test access ports 316, 326 and
336 as shown. The test mode select TMS and test clock TCK signals are
routed to each test access port. The input of the scan chain is test data
in, which is tied to the test data input of test access port 316. The test
data output of test access port 316 is connected to the test data input of
test access port 326. In similar fashion, the test data output of test
access port 326 is connected to the test data input of test access port
336. The test data output of test access port 336 is the test data output
of the scan chain. Functional interconnects 340 may be appropriately
tested by sequentially loading a number of test patterns into the scan
chain formed by integrated circuits 310, 320 and 330, applying the test
pattern, capturing the results, and reading out from the scan chain the
results of each test pattern.
Note that testing assembly 300 requires a knowledge of the interconnect
structure between integrated circuits 310, 320 and 330. This information
is derived from design information describing the system under test. This
design information must include descriptions of the integrated circuit's
boundary scan structure, such as a representation in Boundary Scan
Description Language, and logical descriptions of the interconnect
topology of all interconnect structures within the system under test,
including multi-chip modules, printed wiring boards, backplanes,
connectors, cables, etc. This information must be condensed into a form
that can be used to generate interconnect test patterns. The methods in
accordance with the preferred embodiments disclosed herein assume that a
first sequence of test patterns has been generated using known techniques
that will test the interconnect structure of an assembly such as assembly
300.
Contention During Boundary Scan Testing
Test patterns are generated in a manner that assures that there is never
any steady-state signal contention. However, as described in the
Background of the Invention, it is possible for contention to occur during
boundary scan testing when the scan chain is making a transition from one
test pattern to the next. Driver contention occurs when at least two
driver elements on a particular net attempt to drive the net to opposite
logic values. This situation opens up a low resistance path from power to
ground that can cause drivers to overload and burn out. For example, if a
particular net is being driven high by a first driver during one test
pattern, and the following test pattern drives the same net low by a
different driver, it is possible due to clock skew and differences in
propagation delay that both drivers could attempt for a short period of
time to simultaneously drive the net to opposite states. When both drivers
are on the same scan chain, this contention is relatively short. However,
even short periods of contention can shorted the life of an integrated
circuit if the contention occurs on a regular basis, as would happen if
the interconnect structure is tested using boundary scan testing each time
the assembly is powered up.
In a system that has more than one scan chain, it is possible to have
contention for longer periods of time. Referring to FIG. 4, in an assembly
400 that includes integrated circuits 410, 420 and 430, integrated circuit
410 is on a first scan chain with input test data in 1 TDI1 and output
test data out 1 TDO1, while integrated circuits 420 and 430 are on a
different scan chain with input test data in 2 TDI2 and output test data
out 2 TDO2. Lets assume that in one test pattern, cell C in integrated
circuit 410 is driving its net high while cells G and J are in the
tristate or receive state. Lets also assume that in the following test
pattern, cell G in integrated circuit 420 drives the same net low, while
cells C and J are in the non-driving mode. If the second scan chain
changes to the second test pattern before the first scan chain changes,
contention will result. This contention may be more severe, and depends on
the timing skew between scan chains. One solution would be to use costly
hardware to synchronize the two scan chains. However, even this solution
does not fix the small periods of contention that may result even if the
scan chains are perfectly synchronized or on the same scan chain. In the
best mode of the invention, the methods of the preferred embodiments are
used to eliminate all contention in a system, thereby assuring that no
contention of any kind will exist in the system. However, it is equally
within the scope of the invention to eliminate less than all potential
contentions in a boundary scan test.
Detailed Description
The methods in accordance with the present invention presented herein
assume that a first sequence of test patterns has been generated to test
the interconnect structure of an electronic assembly. The methods of the
preferred embodiments operate on a first sequence of test patterns to
produce a second sequence of test patterns that eliminate some or all of
the transitions between test patterns that could potentially create
contention during boundary scan testing. For the discussion herein, a
transition between test patterns is considered safe if the transition
cannot cause contention. A transition between test patterns that may cause
contention is unsafe.
Referring to FIG. 5, a method 500 in accordance with a first embodiment of
the invention takes an original sequence of test pattern and inserts a
safe test pattern between every two test patterns in the original sequence
to generate a new sequence of test patterns that avoids all contention
during boundary scan testing. Method 500 starts by getting the sequence of
test patterns that have been generated for testing the interconnects on
the system under test (step 510). Next, method 500 generates a safe test
pattern (step 520). The safe test pattern can be derived from the Boundary
Scan Description Language or any other representation that describes the
boundary scan structure for a given integrated circuit. The safe test
pattern places all drivers in a non-driving high impedance state. Finally,
method 500 generates a new sequence of test patterns by inserting the safe
test pattern between each pair of test patterns in the original sequence
of test patterns (step 530). This creates a sequence of test patterns
where each test pattern transition is either to or from a safe pattern
thus eliminating the possibility of contention on transitions between
patterns. Method 500 succeeds at eliminating all contention during
boundary scan testing by driving each net to a high impedance state before
driving it to the next state. If there are N test patterns in the original
sequence, N-1 safe patterns are required, resulting in 2N-1 total test
patterns. This method easily avoids contention without requiring any
analysis of existing test patterns.
While method 500 in accordance with the first embodiment succeeds in
generating a sequence of test patterns that avoid contention during
boundary scan testing, it does so by inserting a relatively large number
of safe patterns. Furthermore, some logic families may not permit the
application of a safe pattern that causes all nets to be undriven or
placed in a high impedance state. For these reasons, a more refined
approach to avoiding contention during boundary scan testing is needed.
With the information describing the boundary scan structure of the chips in
the system under test and a description of the system interconnect
structure, it is possible to analyze a sequence of interconnect test
patterns to determine if the pattern transitions in the sequence could
cause contention. Referring to FIG. 6, a method 600 in accordance with the
second embodiment starts by getting the first sequence of test patterns
for the system under test (step 510). Next, method 600 analyzes the test
patterns and identifies pairs of test patterns that result in unsafe
transitions, i.e., transitions that may potentially cause contention (step
620). This analysis results in identifying the problem areas in the
sequence of test patterns rather than assuming, as does method 500 of the
first embodiment, that all transitions may cause contention. In reality,
the transition between two test patterns A and B is safe if any one of the
following conditions are true for each net.sub.(N) in the system under
test:
1) the driver (or set of drivers) driving net N in pattern A is the same as
the driver (or set of drivers) driving net N in pattern B
2) the value driven on net N in pattern A is identical to the value driven
on net N in pattern B
3) pattern A or pattern B cause N to be undriven
The only time the transition is unsafe is if different drivers are driving
the same net to opposite values in test patterns A and B. For each pair of
test patterns that produces an unsafe transition, method 600 generates a
safe pattern and inserts the safe pattern between the pair (step 630) to
generate a new sequence of test patterns that avoids contention during
boundary scan testing.
Referring to FIG. 7, a method 700 is one suitable implementation of a
portion of step 620 of FIG. 6. Method 700 determines whether or not the
transition between two test patterns A and B is safe by analyzing one pair
of test patterns A and B net by net. First, a counter N that corresponds
to the net number being analyzed is set to 1 (step 710), which means that
the first net in the test pattern is analyzed first. D.sub.A represents
the set of all active (on) drivers for net N in pattern A. D.sub.B
represents the set of active (on) drivers for net N in pattern B. V.sub.A
is the logic value of net N in pattern A, while V.sub.B is the logic value
of net N in pattern B. These definitions are in step 720. Next, the set of
active drivers for net N in pattern A (D.sub.A) is compared against the
set of active drivers for net N in pattern B (D.sub.B) (step 730). If the
same drivers are driving the net in both test patterns (step 730=YES), no
contention can occur, so N is incremented (step 770). The number N is then
compared against the total number of nets to be analyzed (step 780), and
if all nets in test patterns A and B have been analyzed (step 780=YES),
the transition from A to B is declared safe (step 790). If there remain in
test patterns A and B nets that have not yet been analyzed (step 780=NO),
the process is repeated for the next net.
If the set of drivers for net N in pattern A (D.sub.A) are different than
the set of drivers for net N in pattern B (D.sub.B) (step 730=NO), next
the values of the net are compared (step 740). If the values are the same
(step 740=YES), this means that the different drivers are driving the net
to the same logic level, so no contention can occur. If, however, the
drivers are different (step 730=NO) and the values are different (step
740=NO), we next check to see if either pattern A or pattern B place net N
in a high impedance state (step 750). If either of these test patterns put
net N in a high impedance state (step 750=YES), the transition is either
from or to a high impedance state, which cannot cause contention. Only if
the set of drivers is different (step 730=NO), the values are different
(step 740=NO), and neither test pattern drives net N to a high impedance
state (step 750) is the transition from A to B declared to be unsafe (step
760). Note that the transition from A to B is declared to be unsafe as
soon as the first unsafe transition in the test patterns is encountered,
without regard to how many nets may have safe or unsafe transitions. Note
that method 700 of FIG. 7 would have to be repeated for every test pattern
transition in the original sequence of test patterns in step 510 of FIG.
6. Method 700 of FIG. 7 thus provides a way to check two test patterns for
safe transitions during boundary scan testing.
Referring to FIG. 8, a method 800 is one suitable implementation of a
portion of step 630 of FIG. 6. Method 800 is used to generate a safe
pattern I between two test patterns A and B when it has been determined
that the transition from A to B is an unsafe transition. Method 700 of
FIG. 7 is one way to determine if the transition from A to B is unsafe.
First, counter N is set to 1 (step 810). Next, the same definitions in
step 720 are applied in step 820. Next, we determine whether or not
placing the net in a high impedance state is desired (step 830). This
decision may be based on the characteristics of the logic family being
tested, because some logic families prefer to not have any of their nets
in a high impedance state. If the logic family allows the net to be in a
high impedance state (step 830=YES), the value for safe pattern I at that
net N is set to a high impedance state and the set of drivers for I at
that net N is empty (step 832). The net number N is incremented (step
860), checked against the total number of nets to be analyzed (step 870),
and if all nets have been analyzed (step 870=YES), method 800 is done
(step 880), and the generated safe pattern I is inserted between test
patterns A and B. If all nets have not yet been analyzed (step 870=NO),
the analysis proceeds for the next net. Note that when step 832 is
followed for each net in the system under test, the generic safe test
pattern of step 520 of method 500 (FIG. 5) is generated.
If the logic family does not allow the net to be in a high impedance state
(step 830=NO), method 800 then dynamically determines a safe transition
between A and B for net N depending on the set of drivers driving net N,
the values on net N, and whether we want the value or driver to change
during the intermediate pattern I. If the values in pattern A and pattern
B for net N are the same (step 834=YES) and the set of drivers for pattern
A and pattern B for net N are the same (step 836=YES), there is no
contention. At this point, if for some reason it is desired to change the
net value during the intermediate pattern (step 838=YES), V.sub.1 is set
equal to the complement of V.sub.B, and D.sub.I is set to D.sub.B (step
840). If the net value is to remain the same, V.sub.I is set equal to
V.sub.B, and D.sub.I is set to any nonempty set of drivers on net N (step
844). Because the values are the same, the set of drivers driving the net
doesn't matter, so long as there is at least one driver driving net N. If
the values are the same (step 834=YES) but the drivers are different (step
836=NO), there can still be no contention, so V.sub.I is set equal to
V.sub.B, and D.sub.I is set to any nonempty set of drivers on net N (step
844).
If the values are different (step 834=NO) and the sets of drivers are the
same (step 842=YES), V.sub.I is set equal to either V.sub.A or V.sub.B,
and D.sub.I is set to D.sub.B (step 846). If the drivers are the same,
there can be no contention, so the value assigned to V.sub.I doesn't
matter so long as the set of drivers D.sub.I for net N remains the same.
The potential contention occurs when the present net cannot be tristated
(step 830=NO), the values are different (step 834=NO) and the set of
drivers driving net N are different (step 842=NO). At this point we make
an arbitrary decision of whether to change the driver first or whether to
change the data first (step 848). If the driver is to be changed first
(step 848=YES), V.sub.I is set equal to V.sub.A, which keeps the data the
same from test pattern A to test pattern I, and D.sub.I is set to D.sub.B,
which changes the set of drivers for intermediate test pattern I to match
test pattern B (step 850). If the value is to be changed first (step
848=NO), V.sub.I is set equal to V.sub.B, which changes the data from test
pattern A to test pattern I, and D.sub.I is set to D.sub.A, which keeps
the set of drivers the same for test pattern A and intermediate test
pattern I (step 852). Intermediate test pattern I is constructed net by
net by looping through method 800.
Note that method 800 has been represented very broadly to cover a wide
range of implementation possibilities. In practical terms, some of the
decisions probably don't need to be made. For example, if the values and
set of drivers are the same for a particular net N, as would happen when
steps 834 and 836=YES, V.sub.I could be set to V.sub.A, and D.sub.I could
be set to D.sub.A, rather than determining if the net value should change
in step 838. Similarly, if the values are different (step 834=NO) and the
set of drivers is different (step 842=NO), the decision of whether to
change the driver first or the value first (step 848) probably need not be
made. Either the value may be changed first, or the drivers may be changed
first. Either way avoids contention, and only one need actually be
implemented in generating intermediate test pattern I. Method 800 allows
the generation of a safe test pattern I between test patterns A and B for
a variety of different conditions, some of which may not apply depending
on the particular application. Any possible safe pattern between test
pattern A and B will be generated by some variation of method 800. Note
that in step 630 of FIG. 6, method 800 will be repeated for each pair of
test patterns that have an unsafe transition, and each resulting safe test
pattern I will be inserted between the two test patterns that previously
caused an unsafe transition. While the first embodiment creates a single
safe pattern that puts all nets in a high impedance state, the second
embodiment custom-crafts a multitude of safe patterns that depend on the
patterns that were generating an unsafe transition. The second embodiment
thus improves on the first embodiment by analyzing the original test
patterns for unsafe transitions, and by intelligently inserting only the
number of safe test patterns needed to fix the unsafe transitions.
Referring now to FIG. 9, a method 900 in accordance with a third embodiment
of the invention further improves on the second embodiment by performing
reordering of the test patterns to eliminate some unsafe transitions,
rather than just generating and inserting a safe test pattern everywhere
that an unsafe transition occurs. Method 900 begins by getting the first
sequence of test patterns (step 510). These test patterns are then
reordered to eliminate one or more unsafe transitions (step 920). Any
remaining unsafe transitions are then fixed by producing a safe test
pattern for each unsafe transition (step 930).
Referring to FIG. 10, a method 1000 is a suitable method for reordering
test patterns and generating safe test patterns for steps 920 and 930 of
FIG. 9. Method 1000 begins by constructing a safe transition graph for a
given test pattern sequence (step 1010). The details of how the safe
transition graph is constructed are discussed below with reference to FIG.
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