High speed input buffer - Patent Review 5910920

Claims

What is claimed is:

1. An input buffer circuit adapted to be coupled to a high speed data bus, the input buffer circuit comprising:

a differential sense amplifier circuit selectively coupled to a data input and an internal output node that is adapted to be selectively coupled to a pre-selected voltage level that is a termination voltage of the high speed data bus;

an equilibration circuit connected to the differential sense amplifier circuit for equilibrating the differential sense amplifier circuit in response to an equilibrate signal;

isolation circuitry for selectively isolating the data input node from the differential sense amplifier circuit in response to a sample signal; and

sense amplifier activation circuitry for activating the differential sense amplifier circuit in response to a sense signal is a termination voltage of the high speed data bus.

2. An input buffer circuit adapted to be coupled to a high speed data bus, the input buffer circuit comprising:

a differential sense amplifier circuit selectively coupled to a data input and an internal output node;

an equilibration circuit connected to the differential sense amplifier circuit for selectively equilibrating the differential sense amplifier circuit to a pre-selected bias voltage level in response to an equilibrate signal;

isolation circuitry for selectively isolating the data input node from the differential sense amplifier circuit in response to a sample signal; and

sense amplifier activation circuitry for activating the differential sense amplifier circuit in response to a sense signal.

3. The input buffer circuit of claim 2 wherein the pre-selected bias voltage level is a termination voltage of the high speed data bus.

4. An integrated circuit containing an input buffer circuit adapted to be coupled to a high speed data bus, the integrated circuit comprising:

a differential sense amplifier circuit selectively coupled to a data input and an internal output node;

an equilibration circuit connected to the differential sense amplifier circuit for equilibrating the differential sense amplifier circuit in response to an equilibrate signal;

isolation circuitry for selectively isolating the data input node from the differential sense amplifier circuit in response to a sample signal;

sense amplifier activation circuitry for activating the differential sense amplifier circuit in response to a sense signal; and

a clock input node for receiving an externally provided clock signal; and a phase generation circuit connected to the clock input node, the phase generation circuit producing the equilibrate signal, the sample signal, the sense signal and the latch signal.

5. The integrated circuit of claim 4 wherein the integrated circuit is a dynamic random access memory (DRAM).

6. An integrated circuit comprising an input buffer adapted to be coupled to a high speed data bus for receiving an analog data signal, the input buffer circuit comprising:

a clock input node for receiving an externally provided clock signal;

a phase generation circuit connected to the clock input node, the phase generation circuit producing internal control signals;

first and second receiver circuits selectively coupled to the high speed data bus for alternately decoding the analog data signal in response to the control signals, each receiver circuit comprising:

a differential sense amplifier circuit selectively coupled to a data input and an internal output node;

an equilibration circuit connected to the differential sense amplifier circuit for equilibrating the differential sense amplifier circuit in response to an equilibrate signal;

isolation circuitry for selectively isolating the data input node from the differential sense amplifier circuit in response to a sample signal; and

sense amplifier activation circuitry for activating the differential sense amplifier circuit in response to a sense signal.

7. The integrated circuit of claim 6 further comprising:

a first latch circuit coupled to the differential sense amplifier circuit of the first receiver circuit, the first latch circuit adapted to latch a data state of the first receiver circuit in response to a latch signal; and

a second latch circuit coupled to the differential sense amplifier circuit of the second receiver circuit, the second latch circuit adapted to latch a data state of the second receiver circuit in response to a latch signal.

8. The integrated circuit of claim 6 wherein the integrated circuit is a dynamic random access memory (DRAM).

9. The integrated circuit of claim 6 wherein the equilibrate voltage is one-half of the difference between an upper supply voltage (Vdd) and a lower supply voltage (Vss).

10. The integrated circuit of claim 6 further comprising a vernier adjustment circuit for adjusting the phase generation circuit to maximize valid data receipt, such that data sampling is conducted when valid analog data signals are present on the high speed data bus and not limited to an edge transition of the externally provided clock signal.

11. An integrated circuit comprising an input buffer adapted to be coupled to a high speed data bus for receiving an analog data signal, the input buffer circuit comprising:

a clock input node for receiving an externally provided clock signal;

a phase generation circuit connected to the clock input node, the phase generation circuit producing internal control signals;

a plurality of N-buffer circuits selectively coupled to the high speed data bus for alternately decoding the analog data signal in response to the control signals, each of the N-buffer circuits comprising:

a differential sense amplifier circuit selectively coupled to a data input and an internal output node;

an equilibration circuit connected to the differential sense amplifier circuit for equilibratin