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Integrated circuit I/O using a high performance bus interface    
United States Patent5915105   
Link to this pagehttp://www.wikipatents.com/5915105.html
Inventor(s)Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
AbstractThe present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
   














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Drawing from US Patent 5915105
Integrated circuit I/O using a high performance bus interface - US Patent 5915105 Drawing
Integrated circuit I/O using a high performance bus interface
Inventor     Farmwald; Michael (Berkeley, CA); Horowitz; Mark (Palo Alto, CA)
Owner/Assignee     Rambus Inc. (Mountain View, CA)
Patent assignment
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Publication Date     June 22, 1999
Application Number     08/979,127
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     November 26, 1997
US Classification     710/305 365/233
Int'l Classification     G06F 012/00
Examiner     Auve; Glenn A.
Assistant Examiner    
Attorney/Law Firm     Steinberg; Neil A. Jones, Volentine, Steinberg & Whitt, L.L.P.
Address
Parent Case     This is a continuation of application Ser. No. 08/762,139, filed Dec. 9, 1996, now U.S. Pat. No. 5,809,263, which is a continuation of application Ser. No. 08/607,780, filed Feb. 27, 1996, now abandoned, which is a continuation of application Ser. No. 08/222,646, filed Mar. 31, 1994, which has issued as U.S. Pat. No. 5,513,327, which is a continuation of application Ser. No. 07/954,945, filed Sep. 30, 1992, which has issued as U.S. Pat. No. 5,319,755, which is a continuation of application Ser. No. 07/510,898, filed Apr. 18, 1990, now abandoned.
Priority Data    
USPTO Field of Search     395/556 395/309 365/233 365/230.03 365/233.5 711/100 711/111
Patent Tags     integrated circuit i/o high performance bus interface
   
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