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Synchronous clock generator including delay-locked loop    
United States Patent5920518   
Link to this pagehttp://www.wikipatents.com/5920518.html
Inventor(s)Harrison; Ronnie M. (Boise, ID); Keeth; Brent (Boise, ID)
AbstractA data and command latching circuit includes a delay-locked loop driven by a continuous reference clock signal that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit also includes a variable delay circuit external to the delay-locked loop that is driven by a discontinuous reference clock signal. Delay of the external delay circuit is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal. The delayed clock signals from the delay-locked loop activate control data latches to latch control data arriving at the latch circuit. The delayed signals from the variable voltage circuit activate data latches to latch data arriving at the latch circuit.
   














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Drawing from US Patent 5920518
Synchronous clock generator including delay-locked loop - US Patent 5920518 Drawing
Synchronous clock generator including delay-locked loop
Inventor     Harrison; Ronnie M. (Boise, ID); Keeth; Brent (Boise, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
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Publication Date     July 6, 1999
Application Number     08/799,661
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     February 11, 1997
US Classification     365/233 327/155 327/158 365/194
Int'l Classification     G11C 007/10
Examiner     Dinh; Son T.
Assistant Examiner    
Attorney/Law Firm     Seed and Berry LLP
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Priority Data    
USPTO Field of Search     365/233 365/194 365/189.05 365/189.07 327/155 327/156 327/158 327/161
Patent Tags     synchronous clock generator including delay-locked loop
   
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