Method and apparatus for linear transmission by direct inverse modeling

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method for compensating for distortion caused by a power amplifier in a radio frequency (RF) transmitter, the method comprising:

obtaining an output signal sample that depends on an output signal of the power amplifier;

obtaining an input signal sample that depends on an input signal to the power amplifier;

determining a complex predistortion gain by forming a direct inverse model, wherein the direct inverse model receives the output signal sample and outputs the input signal sample, wherein said complex predistortion gain is a function of a complex gain of the direct inverse model; and

applying said complex predistortion gain to a modulation signal sample to obtain a predistorted signal sample, wherein said complex predistortion gain compensates for distortion caused by the power amplifier when said power amplifier amplifies said input signal.

2. The method of claim 1 wherein said input signal sample depends on a prior modulation signal sample previously processed by the RF transmitter, said prior modulation signal sample and said modulation signal sample each having an instantaneous power within a predetermined range.

3. The method of claim 2 further comprising forming a table of complex predistortion filter coefficients indexed by predetermined ranges of modulation signal sample instantaneous power.

4. The method of claim 1 wherein said input signal sample depends on a prior modulation signal sample previously processed by the RF transmitter, said prior modulation signal sample and said modulation signal sample each having a magnitude within a predetermined range.

5. The method of claim 4 further comprising forming a table of complex predistortion filter coefficients indexed by predetermined ranges of modulation signal sample magnitude.

6. The method of claim 1 wherein said output signal sample is generated by the RF transmitter in processing said input signal sample.

7. The method of claim 1 wherein said modulation signal sample is an amplitude modulated signal sample.

8. The method of claim 7 wherein said amplitude modulated signal sample is a quadrature amplitude modulated signal sample.

9. The method of claim 1 wherein said modulation signal sample is a CPFSK modulated signal sample.

10. The method of claim 1 wherein said output signal sample is obtained by sampling, downconverting and digitizing said output signal of the power amplifier.

11. The method of claim 1 wherein said complex predistortion gain is a weighted average of the complex gain of the filter block and a previous complex predistortion gain.

12. A method for compensating for distortion caused by a power amplifier in a radio frequency (RF) transmitter, the method comprising:

determining an inverse transfer characteristic of the power amplifier as a function of a current signal sample and of a previous signal sample outputted by the RF transmitter; and

applying said inverse transfer characteristic to a modulation signal sample to be amplified by the power amplifier to form a predistorted signal sample, wherein said inverse transfer characteristic compensates for distortion caused by the power amplifier when said power amplifier amplifies a signal dependent on said predistorted signal sample.

13. The method of claim 12 wherein said inverse transfer characteristic is a function of a magnitude of said current signal sample and an average of previous signal sample magnitudes.

14. The method of claim 12 wherein said inverse transfer characteristic is a function of a power of said current signal sample and an average of previous signal sample powers.

15. An apparatus for compensating for distortion caused by a power amplifier of a radio frequency (RF) transmitter, the apparatus comprising:

means for obtaining an output signal sample that depends on an output signal of the power amplifier;

means for obtaining an input signal sample that depends on an input signal to the power amplifier;

means for determining a complex predistortion gain by forming a direct inverse model, wherein the direct inverse model receives the output signal sample and outputs the input signal sample, said complex predistortion gain being a function of a complex gain of the direct inverse model; and

means for applying said complex predistortion gain to a modulation signal sample to obtain a predistorted signal sample, wherein said complex predistortion gain compensates for distortion caused by the power amplifier when said power amplifier amplifies said input signal.

16. The apparatus of claim 15 wherein said input signal sample depends on a prior modulation signal sample previously processed by the RF transmitter, said prior modulation signal sample and said modulation signal sample each having a power within a predetermined range.

17. The apparatus of claim 16 wherein said means for applying said complex predistortion gain includes a table of complex predistortion gains, said table being indexed by predetermined ranges of modulation signal sample power.

18. The apparatus of claim 15 wherein said input signal sample depends on a prior modulation signal sample previously processed by the RF transmitter, said prior modulation signal sample and said modulation signal sample each having a magnitude within a predetermined range.

19. The apparatus of claim 18 wherein said means for applying said complex predistortion gain includes a table of complex predistortion gains indexed by predetermined ranges of modulation signal sample magnitude.

20. The apparatus of claim 15 wherein said output signal sample is generated from said input signal sample.

21. The apparatus of claim 15 wherein said modulation signal sample is an amplitude modulated signal sample.

22. The apparatus of claim 21 wherein said amplitude modulated signal sample is a quadrature amplitude modulated signal sample.

23. The apparatus of claim 15 wherein said modulated signal sample is a FSK modulated signal sample.

24. The apparatus of claim 15 wherein said means for obtaining said output signal sample samples, downconverts and digitizes said output signal of the power amplifier.

25. The apparatus of claim 15 wherein said means for determining a complex predistortion gain further comprises means for determining a weighted average of the complex gain of the filter block and a previous complex predistortion gain.

26. An apparatus for compensating for distortion caused by a power amplifier in a radio frequency (RF) transmitter, the apparatus comprising:

means for determining an inverse characteristic of the distortion caused by the power amplifier as a function of a current signal sample and of a previous signal sample output by the RF transmitter; and

means for applying said inverse characteristic to said current signal sample to form a predistorted signal sample, wherein said inverse characteristic compensates for distortion caused by the power amplifier when said power amplifier amplifies a signal dependent on said predistorted signal sample.

27. The apparatus of claim 26 wherein said inverse characteristic is a function of a magnitude of said current signal sample and an average of previous signal sample magnitudes.

28. The apparatus of claim 26 wherein said inverse characteristic is a function of a power of said current signal sample and an average of previous signal sample powers.

29. A system for compensating for distortion caused by a power amplifier in a radio frequency (RF) transmitter, the system comprising:

a predistorter coupled to said power amplifier, wherein said predistorter is configured to apply an inverse characteristic to a modulation signal, wherein said inverse characteristic is a function of a modulation signal level of the modulation signal and of a modulation signal level of a previous modulation signal, wherein said modulation signal is modulated according to a first modulation scheme; and

a trainer coupled to said predistorter and said power amplifier, wherein said trainer is configured to provide inverse characteristics to said predistorter, said inverse characteristics being a function of a level of a power amplifier output signal and of a previous power amplifier output signal level, wherein said inverse characteristics compensate for distortion caused by the power amplifier.

30. The system of claim 29 wherein said modulation signal level and said power amplifier output signal level are instantaneous powers of said modulation signal and said power amplifier output signal.

31. The system of claim 29 wherein said modulation signal level and said power amplifier output signal level are magnitudes of said modulation signal and said power amplifier output signal.

32. The system of claim 29 wherein said function of a modulation signal level and of a previous modulation signal level is a function of said modulation signal level and of a plurality of previous modulation signal levels.

33. The system of claim 29 wherein said modulation and power amplifier signals are digital signals.

34. The system of claim 29 wherein said inverse characteristic includes a first gain and a second gain, said first gain being a function of said modulation signal level and said second gain being a function of said previous modulation signal level.

35. The system of claim 34 wherein said function of a modulation signal level and of a previous modulation signal level is a function of a product of said modulation signal and said first gain, summed with a product of said second gain and an average of said modulation signal level and said previous modulation signal level.

36. The system of claim 35 wherein said predistorter comprises:

a digital filter coupled to receive said modulation signal; and

a table storing filter coefficients indexed by said modulation signal level, said filter coefficients causing said digital filter to implement said first gain and said second gain as a function of said modulation signal level and of said previous modulation signal level.

37. The system of claim 36 wherein said digital filter includes an envelope digital filter configured to provide said average of said modulation signal level and said previous modulation signal level.

38. The system of claim 36 wherein said predistorter further comprises a second table storing filter coefficients indexed by said modulation signal level, said filter coefficients causing said digital filter to implement said first gain and said second gain as a function of said modulation signal level and of said previous modulation signal level, for use with a modulation signal modulated according to a second modulation scheme.

39. The system of claim 38 wherein said predistorter further comprises a third table storing filter coefficients indexed by said modulation signal level, said filter coefficients causing said digital filter to implement said first gain and said second gain as a function of said modulation signal level and of said previous modulation signal level when said modulation signal is to be amplified by the power amplifier while said RF transmitter is being ramped up.

40. The system of claim 38 wherein said predistorter further comprises a fourth table storing filter coefficients indexed by said modulation signal level, said filter coefficients causing said digital filter to implement said first gain and said second gain as a function of said modulation signal level and of said previous modulation signal level when said modulation signal is to be amplified by the power amplifier while said RF transmitter is being ramped down.

41. The system of claim 36 wherein said predistorter further comprises fifth and sixth tables respectively storing filter coefficients indexed by modulation signal level when said RF transmitter is being ramped up and ramped down.

42. A RF transmitter comprising:

a modulator configured to receive an input data signal;

a predistorter coupled to said modulator, said predistorter having a memory effect compensator, said predistorter configured to apply an inverse transfer characteristic to said input data signal so as to provide a predistorted signal corresponding to said input data signal;

a power amplifier coupled to said predistorter, said power amplifier configured to provide an RF output signal corresponding to said predistorted signal;

a coupler coupled to said power amplifier, said coupler configured to provide a feedback signal corresponding to said RF output signal; and

a trainer coupled to said predistorter and said coupler, said trainer having a direct inverse modeler, said trainer configured to provide said inverse transfer characteristic to said predistorter.

43. The RF transmitter of claim 42 wherein said memory effect compensator is configured to apply said inverse characteristic as a function of an instantaneous power of said input data signal and an average of instantaneous powers of previous input data signals.

44. The RF transmitter of claim 42 wherein said memory effect compensator is configured to apply said inverse characteristic as a function of a magnitude of said input data signal and an average of magnitudes of previous input data signals.

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FIELD OF THE INVENTION

The present invention relates to linear transmitters and, more particularly, to linear transmitters using predistortion.

BACKGROUND

It is well-known that the power amplification stages of typical radio frequency (RF) broadcast transmitters behave in a nonlinear fashion when operated near peak capacity. One simple solution to this problem is to "back off" the power amplifier and only operate the power amplifier below saturation in its linear region. However, backing off the power amplifier tends to reduce the power conversion efficiency of the power amplifier. Additionally, for a given required transmitter output power, the power amplifier used must be larger (and more expensive) than a power amplifier that can be operated at peak capacity.

Furthermore, although backing off would allow the power output of the power amplifier to behave more linearly, backing off would not alleviate the phase distortion of the power amplifier. For modulation schemes that only depend upon modulation of amplitude (such as AM), phase distortion is of relatively little concern. However, for other types of modulation schemes that rely upon both amplitude and phase modulation, phase distortion is an important concern.

An alternative solution, commonly referred to as predistortion, compensates for the distortion caused by the power amplifier by "predistorting" the signal to be amplified with the "inverse" of the transfer characteristic of the power amplifier. FIG. 1 is a simplified block diagram of an exemplary conventional predistortion subsystem 100 for use in a transmitter. A predistorter 101 is coupled to receive a modulation signal to be amplified by a power amplifier 103 and broadcast through an antenna 105. The predistorter 101 operates on the received modulation signal to predistort the modulation signal with the calculated inverse of the transfer characteristic of the power amplifier 103. Thus, ideally, the "predistortion" and the power amplifier distortion cancel each other out to achieve a linear amplification of the output signal. In this example, the predistortion subsystem 100 includes a trainer 107 to monitor the power amplifier input and output signals to determine the distortion caused by the power amplifier 103, which may change over time. The trainer 107 then provides signals to update the predistorter 101 so that predistorter 101 tracks any changes in the transfer characteristic of the power amplifier 103.

FIG. 2 is a simplified block diagram of the conventional predistorter 101 (FIG. 1). Typical conventional predistortion schemes attempt to model the performance of the power amplifier and calculate the "inverse" of the amplifier transfer characteristic. All of the predistortion schemes known to the inventors of the present invention attempt to model the power amplifier performance as a function of the instantaneous power or magnitude envelope of the input signal to the power amplifier. Accordingly, these conventional predistortion schemes predistort the input signal as a function of the power or magnitude of the signal to be amplified. For example, U.S. Pat. No. 4,291,277 issued to Davis et al. and U.S. Pat. No. 5,049,832 issued to Cavers disclose such a scheme. Thus, in this scheme, the predistorter 101 includes a power calculator 201 for calculating the instantaneous power or magnitude of the received modulation signal. The calculated instantaneous power or magnitude is then used to access a look-up table (LUT) 203 that stores a corresponding complex value for this particular instantaneous power or magnitude. This complex value approximates the local inverse of the transfer characteristic of the power amplifier for this particular instantaneous power or magnitude of the modulation signal. The LUT 203 can be periodically updated by the trainer 107 (FIG. 1) so that the complex values reflect any changes in the transfer characteristic of the power amplifier 103 (FIG. 1). The LUT 203 provides this complex value to a multiplier 205, which multiplies the modulation signal with this complex value to predistort the modulation signal. Thus, when the predistorted modulation signal is subsequently amplified by the power amplifier, the predistortion cancels to some extent the distortion caused by the power amplifier.

Although these conventional predistortion schemes represent an improvement over earlier schemes to reduce power amplifier distortion, the inventors of the present invention have observed that modeling the power amplifier transfer characteristic using only the instantaneous power or magnitude does not completely accurately predict the distortion caused by the power amplifier. Consequently, predistortion schemes based on such models cannot completely correct the distortion caused by the power amplifier.

FIG. 3 is a flow chart illustrative of a conventional process of calculating the complex values that are stored in the LUT 203 (FIG. 2). In a step 301, the trainer 107 (FIG. 1) determines the instantaneous magnitude and phase of the input signal to the power amplifier 103 (FIG. 1) and the instantaneous magnitude and phase of the amplified (and distorted) output signal. The trainer 107 typically stores these values in a LUT (not shown) within the trainer and, thus, can directly model the transfer characteristics of the power amplifier 103. In step 302, these characteristics are stored in a first lookup table (LUT). This first trainer LUT is indexed using the actual amplifier output power or magnitude. Then in a next step 303, the trainer 107 calculates the mathematical "inverse" of the transfer characteristic of the power amplifier. This step is generally computationally intensive, thereby undesirably increasing the complexity of the hardware and software of the trainer 107 and consuming processing time and power. In addition, because the trainer LUT is indexed by actual amplifier output power or magnitude, addressing errors may occur because the amplifier output signal is potentially noisy. Then in a step 305, the trainer stores the calculated inverse in the second LUT 203 of the predistorter 101.

In view of the above shortcomings of conventional predistortion schemes, there is a need for a predistortion system that will compensate for power amplifier distortion more accurately than the conventional predistortion systems that are based on instantaneous envelope power or magnitude. There is also a need for a less complex and more accurate scheme to provide the inverse of the power amplifier transfer characteristic.

SUMMARY

In accordance with the present invention, a system for linearly transmitting an amplified output signal using predistortion is provided. In one embodiment adapted for use with digital input data, the system uses a direct inverse modeling scheme to more easily and accurately determine the inverse of the transfer characteristic of a power amplifier of a RF transmitter. In this embodiment, the "inverse" of the transfer characteristic of the power amplifier is directly modeled by considering the power amplifier as a signal processing block with the input and output ports reversed. More specifically, the output signal of the power amplifier is considered the input signal of the "inverse" power amplifier model and, correspondingly, the modulated input signal of the power amplifier is considered the output signal of the "inverse" power amplifier model. As a result, the computationally intensive inversion required by the conventional schemes is avoided, which serves to free up resources and reduce processing time and power consumption. Further, unlike the conventional inverse modeling schemes, the direct inverse modeling scheme of the present invention indexes the LUT using the modulated input signal samples instead of the potentially noisier output signal samples, which helps to increase the accuracy of the predistortion. The trainer subsystem of the predistortion scheme stores complex coefficients in the LUT, which are then used as the tap weights of a digital non-linear filter implementing the predistorter.

In another aspect of the present invention, the predistortion LUT is addressed using values that are functions of not only the instantaneous envelope power or magnitude, but also past power or magnitude envelopes. That is, the predistortion system takes into account the instantaneous envelope power or magnitude of the current sample and a profile of the envelope power or magnitude of previous samples to accurately compensate for modulation envelope memory effects of the power amplifier. The past powers or magnitudes provide an indication of the trajectory of the power or magnitude leading to the current power or magnitude, which enables the predistorter to more accurately compensate for the power amplifier distortion. The predistorter LUT is updated with values that can be indexed by this profile of past powers or magnitudes as well as the instantaneous power or magnitude in a two-dimensional table. In a further refinement of the invention, other parameters may be used to index multi-dimensional LUTs. In this aspect of the invention, the trainer updates the predistorter LUT using the same methodology (i.e., taking into account the past power or magnitude profile and other parameters).

In yet another aspect of the present invention, the trainer analyzes the training data before using the data to update the predistorter LUT. More specifically, the trainer first qualifies the data to screen out unreliable data and to ensure a statistically valid number of samples of a particular memory slot of the predistorter LUT. Memory slots without qualifying data are filled with interpolated values derived from neighboring memory slots. In a further refinement of this aspect of the invention, the predistorter LUT is updated by filtering the current updates with weighted contributions of past updates instead of simply overwriting the LUT with the new values.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a conventional predistortion system;

FIG. 2 is a block diagram of a conventional predistorter as depicted in FIG. 1;

FIG. 3 is a flow diagram of a conventional process to calculate the complex values of the predistorter depicted in FIG. 2;

FIG. 4 is a block diagram of a transmitter using a predistortion system according to one embodiment of the present invention;

FIG. 5 is a block diagram of a predistortion system according to one embodiment of the present invention;

FIG. 5A and FIG. 5B are block diagrams illustrating direct inverse modeling according to one embodiment of the present invention;

FIG. 6 is a more detailed block diagram of the predistortion system depicted in FIG. 5;

FIG. 7 is a block diagram of a predistortion filter according to one embodiment of the present invention;

FIG. 8 is block diagram of a predistortion filter according to a second embodiment of the present invention;

FIG. 9 is a block diagram of an envelope filter according to one embodiment of the present invention;

FIG. 9A is a block diagram of an envelope filter according to a second embodiment of the present invention;

FIG. 10 is a block diagram of an envelope filter according to a third embodiment of the present invention;

FIG. 10A is a block diagram of an envelope filter according to a fourth embodiment of the present invention;

FIG. 11 is a functional block diagram of a look-up table address generator according to one embodiment of the present invention;

FIGS. 12, 12A and 12B are functional block diagrams of a trainer according to different embodiments of the present invention;

FIG. 13 is a functional block diagram of the solver depicted in the trainer of FIG. 12, according to one embodiment of the present invention;

FIGS. 13A and 13B are flow diagrams illustrating the operation of the solver according to two embodiments of the present invention; and

FIG. 14 is a block diagram of digital signal processing circuit for implementing a predistorter and trainer, according to one embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 4 is a functional block diagram of a linear transmitter 400 using a predistortion system according to one embodiment of the present invention. This embodiment of the transmitter is substantially similar to the transmitter described in U.S. Pat. No. 5,732,333 to Cot et al, which is commonly assigned to the assignee of the present invention and incorporated herein by reference. In a preferred embodiment, the linear transmitter 400 is adapted for use as a paging transmitter in a paging system, although it can be used in any radio frequency (RF) application.

The transmitter 400, in the forward signal processing path, includes a modulator 403, a predistorter 407, a digital quadrature modulator 411, a digital-to-analog converter 412, an analog upconverter 413, the power amplifier 103 and the transmitting antenna 105. A feedback loop of the transmitter 400 includes a directional coupler 419 (between the power amplifier 103 and the antenna 105), an analog downconverter 423, an analog-to-digital converter 424, a digital quadrature demodulator 425, and a trainer 431. The trainer 431 is coupled to receive the output signals of the digital modulator 403 and interact with the predistorter 407. In other embodiments, additional power amplifiers may be connected in parallel with the power amplifier 103 to increase the gain of the transmitter 400.

Digital data that is to be broadcast by the transmitter 400 is provided to the modulator 403, as represented by an arrow 432. The digital data may be provided by any source. In the preferred embodiment, the digital data received by the modulator 403 is provided from a transmitter controller (not shown) of the paging system. The transmitter controller receives data over a link channel from a paging terminal and formulates the data for transmission. The details of the construction of a transmitter controller, and indeed an entire paging system, can be found in U.S. Pat. No. 5,481,258 to Fawcett et al., U.S. Pat. No. 5,365,569 to Witsaman et al. and U.S. Pat. No. 5,416,808 to Witsaman et al., commonly assigned to the assignee of the present invention and incorporated herein by reference.

In a preferred embodiment, the data is a series of digital symbols, with each symbol representing a predetermined number of bits. The number of bits per symbol is dependent upon the particular modulation scheme being transmitted by the transmitter 400. Modulation formats in typical conventional paging data systems include, for example, two or four tone frequency shift keying (FSK) modulation, continuous phase FSK (CPFSK), 43K75B8E formal modulation (a type of amplitude modulation developed by Motorola) and quadrature amplitude modulation (QAM). QAM formats include, for example, an eight level QAM scheme that would have a three-bit symbol. Similarly, a sixteen level QAM scheme would have four bits per symbol. It will be appreciated that for a three-bit symbol, there are eight possible symbols. Likewise, for a four-bit symbol, there are sixteen possible symbols.

The modulator 403 correlates each particular symbol with predetermined in-phase and quadrature output signals. Thus, for each unique symbol, a different combination of in-phase and quadrature component signals for the base band signal is output by the modulator. In a preferred embodiment, the modulator 403 includes a Texas Instruments TMS320C44 digital signal processor (DSP) microprocessor that is programmed to perform the in-phase and quadrature modulation on the symbols.

Additionally, as each symbol is processed, the modulator 403 does not "instantaneously" transition from one symbol to another. Such an instantaneous change in in-phase and quadrature output signals would result in high frequency harmonics in the system. Instead, by means of digital filtering, a smooth transition between symbols (and therefore in-phase and quadrature output signals) is achieved. One embodiment of this technique which is applicable to an FSK system is disclosed in more detail in U.S. Pat. No. 5,418,818 to Marchetto et al., assigned to the same assignee as the present invention and incorporated herein by reference.

Next, the in-phase and quadrature component signals output by the modulator 403 are input into the predistorter 407. The predistorter 407 is operative to modify the in-phase and quadrature component signals output from the modulator 403 so as to compensate for any distortion that takes place in the power amplifier 103. In accordance with the present invention, the predistorter uses a predistortion scheme that is dependent not only on the instantaneous power or magnitude envelope of the sample, but also on the power or magnitude envelope of the previous samples. By taking into account the power or magnitude envelope of previous samples, the effect of the trajectory leading to the current sample's power or magnitude envelope is also compensated for in the predistortion of the current sample, improving the linearity of the output signal from the power amplifier 103. This predistortion scheme is described further below in conjunction with FIGS. 5-13A.

The output signals of the predistorter 407 are then provided to the digital quadrature modulator 411. The digital quadrature modulator 411 converts the in-phase and quadrature component signals into a single real digital signal. The real digital signal from the digital quadrature modulator 411 is received by a D-A converter 412 that converts the real digital signal to an analog signal, producing an intermediate frequency output signal. For example, the intermediate frequency is approximately 5.6 MHz in a representative embodiment. Because a single D-A converter is used, the distortion caused by the relative delay and amplitude differences introduced in those conventional systems that use separate D-A for in-phase and quadrature signals is substantially eliminated in the transmitter 400.

The intermediate frequency output signal from the D-A converter 412 is provided to the analog upconverter 413, which converts the intermediate frequency signal to a broadcast frequency signal having a frequency within a frequency band of the paging system. For example, the broadcast frequency is approximately 940 MHz in a representative embodiment. The analog upconverter 413 can be any suitable conventional upconverter such as, for example, a mixer receiving a local oscillator signal.

The power amplifier 103 receives the broadcast frequency signal from the analog upconverter 413, amplifies the signal, and provides the amplified signal to the transmitting antenna 105 for transmission. In this embodiment, the power amplifier 103 is substantially similar to the power amplifier disclosed in U.S. Pat. No. 5,694,085 to Walker, assigned to the same assignee as the present invention and incorporated herein by reference. Of course, any suitable power amplifier can be used in other embodiments.

In order to aid in the accurate predistortion of the signal, the feedback loop monitors the amplified signal from the power amplifier 103. The coupler 419 is a conventional directional coupler positioned relatively close to the antenna 105 and is operative to direct a relatively small portion of the output signal from the power amplifier 103 to the analog downconverter 423.

The analog downconverter 423 operates in an opposite manner to the analog upconverter 413. In particular, the analog downconverter 423 lowers the frequency of the receive signal outputted by power amplifier 103 to an intermediate frequency. In a preferred embodiment, this intermediate frequency is substantially the same as the intermediate frequency used in the forward signal processing path. Within the analog downconverter 423, there is a series of filtering, amplification, and mixing with local oscillator signals processes to generate the intermediate frequency signal, as described in the aforementioned U.S. Pat. No. 5,732,333.

Next, the intermediate frequency signal is converted from an analog intermediate frequency signal into a digital signal. This is accomplished by using a conventional A-D converter 424 such as, for example, an Analog Devices AD9026, which samples the intermediate frequency signal and outputs a digital signal representing the sampled intermediate frequency signal. The digital quadrature demodulator 425 performs a digital quadrature demodulation of the digital signals and outputs the in-phase component signal and the quadrature component signal.

The trainer 431 receives the output signals of the digital quadrature demodulator 425. The trainer 431 also periodically receives the output signals from the modulator 403 and the predistorter 407, as described below in conjunction with FIG. 6. Thus, ideally, the trainer 431 receives the equivalent of the exact modulated signal that was intended to be sent (the output signals of the modulator 403) and the signal that was actually transmitted (the output signals of the digital quadrature demodulator 425). This scheme enables the predistorter 407 to associate the distorted output sample to its corresponding input sample so that the predistorter 407 can more accurately compensate for the distortion caused by the power amplifier 103. Typically, the trainer provides one or more "trainer" signals to the predistorter to update the predistorter's response to the in-phase and quadrature signals input to the predistorter as the power amplifier's response changes due to temperature, age, etc.

In addition, the trainer monitors the actual data or voice signals being transmitted to implement the predistortion scheme, as opposed to special sequences (i.e., not normal data or voice signals) as required by some conventional systems. Thus, normal data or voice transmissions need not be interrupted to transmit special data sequences to update the predistorter as in these conventional systems.

In a further refinement, the transmitter 400 may include digital interpolators 405 and 409, and a digital decimator 429. The digital interpolator 405 is connected between the modulator 403 and the predistorter 407, the digital interpolator 409 is connected between the predistorter 407 and the digital quadrature modulator 411, and the digital decimator 429 is connected between the digital quadrature demodulator 425 and the trainer 431. This circuitry provides further upconversion in the forward signal processing path and corresponding downconversion in the feedback path.

In addition, the transmitter 400 includes a synthesizer 435 connected to the analog upconverter 413 and the analog downconverter 423, a phase locked loop (PLL) 437 connected to the digital quadrature modulator 411. An ovenized reference oscillator 433 is connected to both the synthesizer 435 and the PLL 437. This timing circuitry ensures that the modulation, upconversion, downconversion and demodulation are accurately synchronized.

In this embodiment, the output signals of the modulator 403 are the in-phase and quadrature component signals sampled at 80,000 samples per second (80 ksps). The in-phase and quadrature component signals output by the modulator 403 are received by the digital interpolator 405. The digital interpolator 405 operates to increase the effective sampling rate of the received signals by means of digital interpolation. In a preferred embodiment, the digital interpolator 405 outputs the in-phase and quadrature component signals at a rate of approximately 800 ksps and is implemented with a DSP module having a TMS320C44 DSP microprocessor and associated memory, as described below in conjunction with FIG. 14.

The signals output by the interpolator 405 are received by the predistorter 407. The predistorter 407, as previously described, predistorts the received in-phase and quadrature component signals to compensate for the distortion of the power amplifier 103. The predistorted 800 ksps component signals from the predistorter 407 are received by the digital interpolator 409. The digital interpolator 409 operates in a fashion similar to the interpolator 405 to increase the effective sampling rate. Specifically, both the in-phase and quadrature component signals are first upconverted in a first step by a factor of two. Thus, after this first conversion, the effective sampling rate of the component signals is approximately 1.6 Msps. The signals are then upconverted by another factor of two, resulting in an effective rate of approximately 3.2 Msps. Next, these two 3.2 Msps signals are passed to a further interpolator which upconverts them by a factor of seven to approximately 22.4 Msps. Thus, the output signals of the digital interpolator 409 are in-phase and quadrature component signals that have been sampled at 22.4 Msps. The interpolation stages include digital filtering of the base band signals. The implementation of the digital interpolator 409 is described in more detail in the aforementioned U.S. Pat. No. 5,732,333.

The digital quadrature modulator 411 receives the output signals of the digital interpolator 409 and modulates them as previously described using a digital quadrature modulation scheme. In this embodiment, the digital quadrature modulator 411 uses a digital equivalent of a conventional double balanced modulation scheme in conjunction with a 5.6 MHz carrier signal derived from a 22.4 MHz signal provided by the PLL 437. The real digital modulated output signal is then converted to an analog signal by the D-A converter 412. As a result, the D-A converter 412 outputs a 5.6 MHz analog intermediate frequency signal to the analog upconverter 413.

The analog upconverter 413 receives two local oscillator signals provided by the synthesizer 435. In a preferred embodiment in which the broadcast frequency is 940 MHz, the two frequencies provided by the synthesizer 435 are a 36.9 MHz local oscillator signal and a 897.5 MHz local oscillator signal. The analog upconverter 413 receives the local oscillator signals for mixing with the 5.6 MHz intermediate frequency signal in a conventional two-stage mixing scheme. In the first stage of the upconversion, the intermediate signal is mixed with the 36.9 MHz local oscillator signal, and the upper side band of the resulting 42.5 MHz signal is amplified and bandpass filtered before being mixed with the 897.5 MHz local oscillator signal. The resulting upper side band at 940 MHz is bandpass filtered and provided to the power amplifier 103. It will be appreciated by those skilled in the art of linear RF transmitters that to change the frequency of transmission of the transmitter 400, the local oscillator frequencies generated by the synthesizer 435 can be changed. The 940 MHz signal is then amplified by the power amplifier 103 and broadcast through antenna 105 as previously described for transmitter 400.

In a preferred embodiment, the synthesizer 435 is a Phillips SA7025 synthesizer chip. As noted above, the synthesizer 435 controls the variable local oscillator signal for precisely determining the transmit frequency of the signal. The synthesizer 435 uses a reference oscillator 433 that, in a preferred embodiment, is a stable reference at 10 MHz. In this preferred embodiment, this 10 MHz stable reference is obtained from the transmitter controller of a paging base station.

The 940 MHz receive signal from the coupler 419 is provided to the analog downconverter 423, converted to the intermediate frequency of 5.6 MHz, and received by the digital quadrature demodulator 425. The digital quadrature demodulator 425 operates to generate in-phase and quadrature component signals at 22.4 Msps. In a preferred embodiment, the digital quadrature demodulator is implemented using a Xilinx 4003 field programmable gate array (FPGA) that has been configured to perform the digital quadrature demodulation.

The digital decimator 429 receives the output signals of the digital quadrature demodulator 425 and performs a decimation by a factor of twenty-eight to produce 800 ksps complex base band signals. The downconversion is performed, in a preferred embodiment, by two Harris HSP43220 decimating filter chips programmed to decimate by twenty-eight and to filter the base band signals.

The 800 ksps complex base band signals are received by the trainer 431. As previously described, the trainer analyzes the receive signals and the signals from the modulator 403 to control the predistorter 407 to properly compensate for the distortion caused by the power amplifier 103.

Another important feature of the present invention is that all of the processing done by each of the components of FIG. 4 is keyed off synchronous clock signals. By utilizing the same clocking in the demodulation scheme of components 424-429 as is used in the modulation scheme of components 403-412 and trainer 429, it is possible to monitor the transmitted signal quality on each digital sample. The modulation and demodulation are phase locked to one another with adjustment only needed for the delay through the analog and digital stages, including the power amplifier 103.

FIG. 5 is a functional block diagram of a predistortion system 500 according to one embodiment of