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Claims  |
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What is claimed is:
1. A synchronous semiconductor memory device synchronized with an external clock signal formed of a train of pulses to receive a plurality of external signals including a
control signal and an address signal and to output stored data, comprising:
a memory cell array including a plurality of memory cells arranged in a matrix;
internal clock generating means receiving said external clock signal for generating an internal clock signal, said internal clock generating means activating an operation for generating said internal clock signal in response to activation of a
chip select signal which designates enabling a communication of said external signals between said synchronous semiconductor memory device and an external, and inactivating said operation for generating said internal clock signal in response to
inactivation of an internal circuit activating signal which activates an operation for selecting said memory cells;
control means responsive to said external signals for outputting said internal circuit activating signal, and responsive to said internal clock signal and said external signals for controlling a data input/output operation of said synchronous
semiconductor memory device;
select means controlled by said control means, synchronized with said internal clock signal and responsive to said address signal for selecting a corresponding memory cell of said memory cell array; and
data input/output means synchronized with said internal clock signal for receiving and transmitting stored data between said selected memory cell and the external.
2. The synchronous semiconductor memory device according to claim 1, wherein:
said external signals include an external row address strobe signal, an external column address strobe signal and an external write enable signal; and
said control means responsively activates said internal circuit activating signal when said external row address strobe signal is in an active state and said column address signal and said write enable signal are each in an inactive state at an
activating edge of said external clock signal.
3. The synchronous semiconductor memory device according to claim 1, wherein said internal clock generating means includes:
clock input control means controlled by a clock activating signal for starting and stopping outputting said external clock signal externally received;
standby detector means responsive to activation of said chip select signal for activating said clock activating signal, and responsive to inactivation of said internal circuit activating signal for inactivating said clock activating signal; and
clock buffer means receiving and converting an output of said clock input control means into an internal clock signal.
4. The synchronous semiconductor memory device according to claim 3, wherein said standby detector means includes:
a chip select signal buffer responsive to an activating edge of said chip select signal for activating a power-down reset signal;
first pulse generating means responsive to inactivation of said internal circuit activating signal for outputting a power-down set signal with a predetermined pulse length;
a first 2-input NAND gate receiving said clock activating signal at a first input node and said power-down set signal at a second input node; and
a second 2-input NAND gate receiving said power-down reset signal at a first input node and an output of said first 2-input NAND gate at a second input node and outputting said clock activating signal.
5. The synchronous semiconductor memory device according to claim 1, wherein:
said control means outputs a standby designating signal for designating a standby operation of said synchronous semiconductor memory device in response to activation of said chip select signal and said external signals while said internal circuit
activating signal is inactivated; and
said internal clock generating means includes
clock input control means controlled by a clock activating signal for starting and stopping outputting said external clock signal externally received;
standby detector means responsive to activation of said chip select signal for activating said clock activating signal, and responsive to any of inactivation of said internal circuit activating signal and activation of said standby designating
signal for inactivating said clock activating signal; and
clock buffer means receiving and converting an output of said clock input control means into an internal clock signal.
6. The synchronous semiconductor memory device according to claim 5, wherein:
said external signals include an external row address strobe signal, an external column address strobe signal and an external write enable signal; and
said control means responsively activates said standby designating signal when said chip select signal is in an active state and said external row address strobe signal, said column address strobe signal and said write enable signal are each in
an inactive state at an activating edge of said external clock signal.
7. The synchronous semiconductor memory device according to claim 5, wherein said standby detector means includes:
a chip select signal buffer responsive to an activating edge of said chip select signal for activating a power-down reset signal;
first pulse generating means responsive to inactivation of said internal circuit activating signal for outputting a first power-down set signal with a predetermined pulse length;
second pulse generating means responsive to activation of said standby designating signal for outputting a second power-down set signal with a predetermined pulse length;
a 3-input NAND gate receiving said clock activating signal at a first input node, said first power-down set signal at a second input node, and said second power-down set signal at a third input node; and
a 2-input NAND gate receiving said power-down reset signal at a first input node and an output of said 3-input NAND gate at a second input node and outputting said clock activating signal.
8. The synchronous semiconductor memory device according to claim 1, wherein said internal clock generating means includes:
clock input control means controlled by a clock activating signal for starting and stopping outputting said external clock signal externally received;
standby detector means activating said clock activating signal while said internal circuit activating signal is activated, and activating said clock activating signal in response to activation of said chip select signal and inactivating said
clock activating signal in response to inactivation of said chip select signal while said internal circuit activating signal is inactivated; and
clock buffer means receiving and converting an output of said clock input control means into an internal clock signal.
9. The synchronous semiconductor memory device according to claim 8, wherein said standby detector means includes:
a chip select signal buffer responsive to an activating edge of said chip select signal for activating a power-down reset signal;
first pulse generating means responsive to inactivation of said internal circuit activating signal for outputting a first power-down set signal with a predetermined pulse length;
second pulse generating means responsive to an inactivating edge of an internal clock signal generated after activation of said chip select signal, for outputting a second power-down set signal with a predetermined pulse length;
a first 3-input NAND gate receiving said clock activating signal at a first input node, said first power-down set signal at a second input node, and said second power-down set signal at a third input node; and
a second 3-input NAND gate receiving an inverted version of said internal circuit activating signal at a first input node, said power-down reset signal at a second input node, and an output of said first 3-input NAND gate at a third input node,
and outputting said clock activating signal.
10. The synchronous semiconductor memory device according to claim 8, wherein said standby detector means includes;
a chip select signal buffer responsive to activation of said chip select signal and inactivation of an external clock signal for activating a power-down reset signal;
first pulse generating means responsive to inactivation of said internal circuit activating signal for outputting a first power-down set signal with a predetermined pulse length;
second pulse generating means responsive to an inactivating edge of an internal clock signal generated after activation of said chip select signal, for outputting a second power-down set signal with a predetermined pulse length;
a first 3-input NAND gate receiving said clock activating signal at a first input node, said first power-down set signal at a second input node, and said second power-down set signal at a third input node; and
a second 3-input NAND gate receiving an inverted version of said internal circuit activating signal at a first input node, said power-down reset signal at a second input node, and an output of said first 3-input NAND gate at a third input node,
and outputting said clock activating signal.
11. The synchronous semiconductor memory device according to claim 8, wherein said standby detector means includes:
a chip select signal buffer responsive to activation of said chip select signal and to an elapse of a predetermined time period after inactivation of an external clock signal, for activating a power-down reset signal;
first pulse generating means responsive to inactivation of said internal circuit activating signal for outputting a first power-down set signal with a predetermined pulse length;
second pulse generating means responsive to an inactivating edge of an internal clock signal generated after activation of said chip select signal, for outputting second power-down set signal with a predetermined pulse length;
a first 3-input NAND gate receiving said clock activating signal at a first input node, said first power-down set signal at a second input node, and said second power-down set signal at a third input node; and
a second 3-input NAND gate receiving an inverted version of said internal circuit activating signal at a first input node, said power-down reset signal at a second input node, and an output of said first 3-input NAND gate at a third input node,
and outputting said clock activating signal. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a synchronous semiconductor memory device which is synchronized with an external, periodically applied clock signal to receive an external signal. More
specifically, the present invention relates to a randomly accessible, synchronous dynamic random access memory (SDRAM).
2. Description of the Background Art
While dynamic random access memories (DRAMs) used as main memory have been accessed more and more rapidly, their operating speeds still cannot catch up with those of microprocessors (MPUs). It is thus often said that the access time and cycle
time of DRAM are the bottleneck, which degrades the entire performance of systems. In recent years SDRAMs which operate synchronously with a clock signal have been manufactured as main memories for high-speed MPUs.
An SDRAM achieves rapid access by synchronizing with a system clock signal to rapidly access successive bits, e.g., eight bits for each of data input/output terminals. For example, 8-bit data can be successively read in an SDRAM capable of
inputting and outputting data of eight bits (one byte) through data input/output terminals DQ0-DQ7. In other words, data of eight bits multiplied by eight, i.e., data of 64 bits can be read successively.
The number of bits of successively read or written data is referred as burst length, which can be changed by mode register in SDRAM.
In an SDRAM, external control signals, i.e., a row address strobe signal ext./RAS, a column address strobe signal ext./CAS, a column address strobe signal ext./CAS, an address signal Add and the like are received at a rising edge of an external
clock signal Ext.CLK as a system clock, for example.
FIG. 16 is a schematic block diagram showing a configuration of an internal clock generation circuit 2000 which receives external clock signal Ext.CLK and converts it into an internal clock signal int.CLK in a conventional synchronous dynamic
random access memory.
Internal clock generation circuit 2000 includes a clock input terminal 2002 which receives external clock signal Ext.CLK, an NAND circuit 2004 which receives Ext.CLK from clock input terminal 2002 at one input node and a ground potential GND at
the other input node, an inverter 2006 which receives an output from NAND circuit 2004, and a clock buffer circuit 2008 which receives an output from inverter 2006 to generate an internal clock signal int.CLK with a predetermined pulse width.
For the configuration of the conventional internal clock generation circuit 2000, when an SDRAM is in standby state, external clock signal Ext.CLK is constantly input to clock buffer 2008. Thus, even when the SDRAM in standby state, clock buffer
2008 is constantly in operating state, which results in significant electricity consumption. Thus, the electricity consumption of the SDRAM in standby state cannot be reduced.
Meanwhile, a method of reducing electricity consumption in a state other than the power-down mode, e.g., standby state, in an SDRAM has been proposed, for example, in Japanese Patent Laying-Open No. 7-177015. According to this technique, a power
cutting circuit is provided for an external input/output pin of an SDRAM and the power for the input first-stage circuit of the external input/output pin is cut in standby state to reduce electricity consumption. However, the technique relates to
cutting the power for the input initial-stage circuit of the external input/output pin and is not pertinent to a problem to be solved by the present invention, i.e., the reduction of the electricity consumption of the internal clock generation circuit
for more rapidly accessed SDRAMs.
Furthermore, Japanese Patent Laying-Open No. 7-182857 has suggested a method of reducing electricity consumption by allowing refreshing a DRAM which operates according to a clock in a microcomputer system without generating a clock signal in
standby state. However, this technique is not pertinent to the internal clock generation circuit which converts an external clock signal into an internal clock signal in an SDRAM as an application of the present invention, and does not contemplate the
reduction of the electricity consumption of the internal clock generation circuit for more rapidly accessed SDRAMs.
FIG. 17 is a schematic block diagram showing a configuration of an internal clock generation circuit 3000 with an improved configuration of the conventional internal clock generation circuit 2000 shown in FIG. 16.
Internal clock generation circuit 3000 includes clock input terminal 2002 which receives external clock signal Ext.CLK, an NAND circuit 3004 which is connected to clock input terminal 2002 at one input node and also receives a ground potential at
the other input node, an inverter 3006 which receives an output of NAND circuit 3004, a first clock buffer circuit 3008 which receives an output from inverter 3006 to output a first internal clock signal int.CLK-A, and a second clock buffer circuit 3010
which is controlled by a signal .phi..sub.ACT for designating activating an operation of an internal circuit to provide a memory cell selecting operation in response to external control signals, and receives the output from inverter 3006 and outputs a
second internal clock signal int.CLK-B.
More specifically, while signal .phi..sub.ACT attains inactive low level, the conventional internal clock generation circuit 3000 stops the operation for outputting the second internal clock signal int.CLK-B. By contrast, the first internal clock
signal int.CLK-A is constantly generated and external control signals which provide a command for executing the next operation is responsively received.
Thus, while the first internal clock signal int.CLK-A is required to constantly operate to receive a command for specifying the next operation, the second internal clock signal int.CLK-B for controlling the other internal circuit operations is
generated after signal .phi..sub.ACT is activated.
That is, when an SDRAM is in standby state and signal .phi..sub.ACT is inactivated (i.e., at low level), the operation of the second clock buffer 3010 is stopped and thus electricity consumption can be reduced in standby state.
However, the conventional internal clock generation circuit 3000 also requires the first clock buffer circuit 3008 to constantly operate, and sufficient reduction in electricity consumption cannot be achieved in standby state. In addition, the
electricity consumption in the clock buffer circuit in standby state is increased as clock frequency is increased, i.e., as the SDRAM is operated more rapidly, and thus it is more difficult for an SDRAM with higher performance to suppress electricity
consumption.
SUMMARY OF THE INVENTION
One object of the present invention is to provide an SDRAM capable of reducing electricity consumption in standby state.
Another object of the present invention is to provide an SDRAM capable of both low electricity consumption and rapid operation when the SDRAM is rapidly operated by a rapid, external clock signal.
In summary, the present invention contemplates a synchronous semiconductor memory device synchronized with an external clock signal formed of a train of a series of pulses to receive a plurality of external signals including a control signal and
an address signal and output stored data, comprising a memory cell array, an internal clock generation circuit, a control circuit, a select circuit and a data input/output circuit.
The memory cell array has a plurality of memory cells arranged in a matrix. The internal clock generation circuit receives the external clock signal and generates an internal clock signal.
The internal clock generation circuit activates an operation for generating the internal clock signal in response to activation of a chip select signal for designating enabling the communication of the external signals between the synchronous
semiconductor memory device and the external, and inactivates the operation for generating the internal clock signal in response to inactivation of internal circuit activating signal for activating an operation for selecting a memory cell.
The control circuit outputs the internal circuit activating signal in response to the external signals, and controls the data input/output operation of the synchronous semiconductor memory device in response to the internal clock signal and the
external signals. The select circuit is controlled by the control circuit and is synchronized with the internal clock signal to select a corresponding memory cell of said memory cell array in response to an external row address signal. The data
input/output circuit is synchronized with the internal clock signal to transmit and receive stored data between the selected memory cell and the external.
The internal clock generation circuit preferably includes a clock input control circuit which is controlled by a clock activating signal to start and stop outputting the external clock signal received from the external, a standby detection
circuit which activates the clock activating signal in response to activation of the chip select signal and inactivates the clock activating signal in response to inactivation of the internal circuit activating signal, and a clock buffer circuit which
receives and converts an output of said clock input control circuit into the internal clock signal.
In another suitable manner, the control circuit also outputs a standby designating signal for designating the standby operation of the synchronous semiconductor memory device in response to activation of the chip select signal and to the control
signal while the internal circuit activating signal is inactivated, and the internal clock generation circuit includes a clock input control circuit which is controlled by a clock activating signal to start and stop outputting the external clock signal
externally applied, a standby detection circuit which activates the clock activating signal in response to activation of the chip select signal and inactivates the clock activating signal in response to either inactivation of the internal circuit
activating signal or activation of the standby designating signal, and a clock buffer circuit which receives and converts an output of the clock input control circuit into an internal clock signal.
In still another suitable manner, the internal clock generation circuit includes a clock input control circuit which is controlled by a clock activating signal to start and stop outputting the external clock externally applied; a standby
detection circuit which activates the clock activating signal while the internal circuit activating signal is activated, and activates the clock activating signal in response to activation of the chip select signal and inactivates the clock activating
signal in response to inactivation of the chip select signal while the internal circuit activating signal is inactivated; and a clock buffer circuit which receives and converts an output of the clock input control circuit into an internal clock signal.
Therefore a main advantage of the present invention is that an internal clock generation circuit starts the operation for generating an internal clock signal in response activation of a chip select signal and stops the generation of the internal
clock signal in response to inactivation of an internal circuit activating signal and thus electricity consumption can be reduced in standby state.
Another advantage of the present invention is that when such an external signal that the chip select signal is activated and the internal circuit activating signal is not activated is applied in standby state, the internal clock generation
circuit will not start the internal clock generating operation and thus the electricity consumption can further be decreased in standby state.
Still another advantage of the present invention is that when the chip select signal is activated and such an external signal that the internal circuit activating signal is not activated is applied, the internal clock generation circuit will not
shift to the state for providing the internal clock generating operation and thus electricity consumption can be reduced in standby state.
Furthermore, even when a rapid external clock signal is provided for achieving rapid read or write operations of a synchronous semiconductor memory device, the electricity for generating the internal clock signal is not consumed in standby state
and thus low electricity consumption in standby state can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram showing a configuration of an SDRAM 1000 according to a first embodiment of the present invention.
FIG. 2 is a timing chart for illustrating a read operation of SDRAM 1000.
FIG. 3 is a schematic block diagram showing a configuration of a circuit 300 for designating activating an internal circuit.
FIG. 4 is a schematic block diagram showing a configuration of an internal clock generation circuit 200 according to the first embodiment.
FIG. 5 is a schematic block diagram showing a configuration of a clock buffer 206.
FIG. 6 is a timing chart for illustrating an operation of internal clock generation circuit 200.
FIG. 7 is a schematic block diagram showing a configuration of a standby detection circuit 400 according to a second embodiment of the present invention.
FIG. 8 is a timing chart for illustrating a change with time in a control signal for applying a NOP command.
FIG. 9 is a timing chart for illustrating an operation of standby detection circuit 400 according to the second embodiment of the present invention.
FIG. 10 is a schematic block diagram showing a configuration of a standby detection circuit 500 according to a third embodiment of the present invention.
FIG. 11 is a timing chart for illustrating an operation of standby detection circuit 500.
FIG. 12 is a schematic block diagram showing a configuration of an internal clock generation circuit 600 according to a fourth embodiment of the present invention.
FIG. 13 is a timing chart for illustrating an operation of internal clock generation circuit 600.
FIG. 14 is a schematic block diagram showing a configuration of an internal clock generation circuit 700 according to a fifth embodiment of the present invention.
FIG. 15 is a timing chart for illustrating an operation of internal clock generation circuit 700.
FIG. 16 is a schematic block diagram showing a configuration of a conventional internal clock generation circuit 2000.
FIG. 17 is a schematic block diagram for showing a circuit configuration of an improved conventional internal clock generation circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
FIG. 1 is a schematic block diagram showing a configuration of an SDRAM 1000 of the present invention. As has been described above, the SDRAM is synchronized with an external clock signal to perform a synchronous operation for receiving a
control signal and a data signal and thus a margin for data input/output time need not be ensured for the skew (i.e., the timing lag) of address signals. Accordingly, cycle time can be advantageously reduced. Since successive data can be written and
read synchronously with a clock signal, access time can be reduced in successively accessing successive addresses.
Furthermore, as an architecture for rapidly operating an SDRAM, Choi et al. has presented a 2-bit prefetched SDRAM which provides writing/reading data for every two bits (1993 Symposium on VLSI circuit).
Hereinafter, SDRAM 1000 is assumed to have a configuration capable of the 2-bit prefetch operation described above.
It should be noted, however, that, as is apparent from the description hereinafter, the present invention can be more generally applied to reducing the electricity consumption of a synchronous semiconductor memory device which receives an
external clock signal and generates an internal clock signal to control an operation of an internal circuit.
FIG. 1 shows a configuration of a functional portion related to the input/output data corresponding to one bit of an SDRAM with X 16-bit configuration. More specifically, a function block 100 is provided for each data input/output terminal, and
the SDRAM with X 16-bit configuration includes 16 function blocks 100 for their respective input/output terminals. The exemplified function block 100 itself has been generally used in conventional SDRAMs and the configuration and operation thereof will
now be described.
In function block 100 shown in FIG. 1, the memory cell array portion associated with a data input/output terminal DQi includes memory cell arrays 71a and 71a' forming a bank A, and memory cell arrays 71b and 71b' forming a bank B.
Bank A and bank B are divided into memory cell array banks A0 and A1 and memory cell array banks B0 and B1 selected according to address signals, respectively.
Memory cell array banks A0 and A1 are each provided with a group of X decoders 52a including a plurality of row decoders for decoding address signals ext.A0-ext.Ai to select corresponding row of memory cell array 71a, a group of Y decoders 53a
including a plurality of column decoders for decoding internal column address signals Y1-Yk to generate a column select signal for selecting corresponding columns of memory cell array 71a, and a group of sense amplifiers 54a for detecting and amplifying
the data of the memory cells connected to the selected row of memory cell array 71a.
The group of X decoders 52a includes row decoders each provided for each word line of memory cell array 71a. According to internal address signals X0-Xi generated in responsive to external address signals ext.A0-ext.Ai, a corresponding row
decoder selects its respective word line.
The group of Y decoders 53a includes column decoders each provided for a column select line of memory cell array 71a. One column select line selects, for example, four pairs of bit lines. The group of X decoders 52a and the group of Y decoders
53a simultaneously select memory cells of four bits in each of memory cell array banks A0 and A1. The group of X decoders 52a and the group of Y decoders 53a are each activated by a bank designating signal BA.
Memory cell array banks B0 and B1 are each provided with a group of X decoders 52b and a group of Y decoders 53b which are each activated by a bank designating signal BB.
Bank A is also provided with an internal data transmission line (a global I/O line) for transmitting the data detected and amplified by the group of sense amplifiers 54a and for transmitting written data to a selected memory cell in memory cell
array 71a.
Memory cell array bank A0 is provided with a global IO line bus GIO0, and memory cell array bank A1 is provided with a global IO line bus GIO1. One global IO line bus includes four pairs of global IO lines for simultaneously transmitting and
receiving data to and from simultaneously selected memory cells of four bits.
The pairs of global IO lines GIO0 for memory cell array bank A0 are provided for a register 59a for write and a group of write buffers 60a, and the pairs of global IO lines GIO1 for memory cell array bank A1 are provided for a register 59a', for
write and a group of write buffers 60a'.
An input buffer 58a of 1-bit width generates internal written data from the data input from data input/output terminal DQi. A selector 69a, controlled by a selector control signal .phi.SEA output from a second control signal generating circuit
63, switches and inputs an output of input buffer 58a to either register 59a for write or register 59a' for write.
More specifically, input buffer 58a is activated in response to an input buffer activating signal .phi.WDBA to generate internal written data from the data input from data input/output terminal DQi, and selector 69a is controlled in response to
selector control signal .phi.SEA ground-output from the second control signal generating circuit 63 in response to an address signal to output the internal written data to one of registers 59a and 59a' for write.
Registers 59a and 59a' for write is activated in response to register activating signals .phi.RwA0 and .phi.RwA1, respectively, to successively store written data output from selector 69a. The groups of write buffers 60a and 60a' are activated
in response to write buffer activating signals .phi.WBA0 and .phi.WBA1 to amplify the data stored in their respective registers 59a and 59a' for write and transmit the amplified data to the buses of pairs of global IO lines GIO0 and GIO1, respectively.
The double-system pairs of global IO lines GIO0 and GIO1 are commonly provided with an equalizer circuit (not shown) which is activated in response to an equalizer circuit activating signal .phi.WEQA (not shown) to equalize the buses of pairs of
global IO lines GIO0 and GIO1.
The groups of write buffers 60a and 60a' and write registers 59a and 59a' each have a width of eight bits.
Memory cell array bank B similarly includes memory cell array banks B0 and B1 which each include a group of X decoders 52b, a group of Y decoders 53b, a group of sense amplifiers 54b activated in response to a sense amplifier activating signal
.phi.SAB, groups of write buffers 60b and 60b' activated in response to buffer activating signals .phi.WBB0 and .phi.WBB1, registers for write 59b and 59b' activated in response to register activating signals .phi.RWB0 and .phi.RwB1, selectors 69b and
70b controlled by a selector control signal .phi.SEB, and an input buffer 58b activated in response to a buffer activating signal .phi.WDBB.
The configuration of bank A is the same as that of bank B. The provision of registers for write 59a and 59' and 59b and 59b' allows data input/output through one data input/output terminal DQi synchronously with a rapid clock signal.
As to various control signals for banks A and B, only control signals for one of the banks are generated in response to bank designating signals BA and BB.
In a function block for a data read signal, data detected and amplified by the group of sense amplifiers 54a is transmitted on bus GIO of an internal data transmission line (a global IO line) provided for bank A.
Provided for reading data are a read preamplifier 55a activated in response to a preamplifier activating signal .phi.RBA0 for amplifying the data on global IO line bus GIO0 for bank A0, and a register for read 56a activated in response to a
register activating signal .phi.RrA0 for storing the data amplified by read preamplifier 55a.
Also provided are a read preamplifier 55a' activated in response to a preamplifier activating signal .phi.RBA1 for amplifying the data on global IO line bus GIO1 provided for bank A1, and a register for read 56a' activated in response to a
register activating signal .phi.RrA1 for storing the data amplified by read preamplifier 55a'.
Function block 100 shown in FIG. 1 also includes a selector 70a which receives the data from registers 56a and 56a' for read and successively outputs one of the received data in response to selector signal .phi.SEA, and an output buffer 57a which
receives the output from selector 70a and successively output the data.
Read preamplifier 55a and register for read 56a each have a width of four bits for four pairs of global IO lines. Register 56a for read latches and successively outputs the data output from read preamplifier 55a in response to register
activating signal .phi.RrA1.
Read preamplifiers 55a' and register 56' for read operate similarly.
An output buffer 57a is responsive to an output enable signal .phi.OUTA for transmitting 8-bit data successively output from selector for read 70a to data input/output terminal DQi. Although data is input and output via data input/output
terminal DQi in FIG. 1, data may be input and output via separate terminals.
Memory cell array bank B has exactly the same configuration: read preamplifiers 55b and 55b, activated by read preamplifier activating signals .phi.RBB0 and .phi.RBB1, respectively, registers 56b and 56b' for read activated by register activating
signals .phi.RrB0 and .phi.RrB1, respectively, a selector 70b which selectively outputs one of the outputs of registers for read 56b and 56b' in response to signal .phi.SEB, and an output buffer 57b which outputs the output data from selector 70b to data
input/output terminal DQi in response to a signal .phi.OUTB.
Since banks A and B have almost the same configuration and only one of them is selected in response to bank designating signals BA and BB, banks A and B can operate almost independently of each other.
A first control signal generating circuit 62, a second control signal generating circuit 63 and a clock counter 64 are provided as a control system for independently driving banks A and B.
Synchronously with an external clock signal Ext.CLK, the first control signal generating circuit 62 receives externally applied control signals, i.e., an external row address strobe signal ext./RAS, an external column address strobe signal
ext./CAS, a chip select signal ext./CS and an external write enable signal ext./WE, a clock enable signal CKE, and generates internal control signals .phi.xa, .phi.ya, .phi.W, .phi.O, .phi.R and C0.
.phi.O is a signal for designating outputting the control signal .phi.OUTA or .phi.OUTB for directing output buffer 57a or 57b to provide data output operation.
Signal .phi.W indicates that write operation is designated, and signal .phi.R indicates that read operation is designated.
Chip select signal ext./CS indicates that receiving the other control signals is enabled when the signal attains active low level. More specifically, when signal ext./CS attains inactive high level, taking the other control signals into the
first control signal generating circuit 62 is prohibited.
Signal C0 is a one-short pulse signal generated in response to activation of signal ext./CS and in synchronization with internal clock signal int.CLK.
As will be apparent from the following description, combinations of signals ext./RAS, ext./CAS and ext./WE designate the activation, read operation, write operation, precharge operation, refresh operation and the like of SDRAM 1000.
The second control signal generating circuit 63 generates bank designating signals BA and BB, the least significant bit YO of an external address signal, internal control signals .phi.W, .phi.O, .phi.R and C0, and control signals for
independently driving banks A and B in response to an output of clock counter 64, i.e. sense amplifier activating signals .phi.SAA and .phi.SAB, write buffer activating signals .phi.WBA0, .phi.WBA1, .phi.WBB0 and .phi.WBB1, signals for activating the
registers for write .phi.RWA0, .phi.RwA1, .phi.RwB0 and .phi.RwB1, selector control signals .phi.SEA and .phi.SEB, input buffer activating signals .phi.WDBA and .phi.WDBB, read preamplifier activating signals .phi.RBB0, .phi.RBB1, .phi.RBA0 and
.phi.RBA1, signals for activating the registers for read .phi.RrB0, .phi.RrB1, .phi.RrA0 and .phi.RrA1, and output buffer activating signals .phi.OUTA and .phi.OUTB.
SDRAM 1000 further includes as peripheral circuits an X address buffer 65 which is responsive to an internal control signal .phi.xa for receiving external address signals ext.A0-ext.A1 and generating internal address signals X0-Xj and bank
selecting signals BA and BB, and a Y address buffer 66 activated in response to an internal control signal .phi.ya for outputting internal column address signals Y0-Yk for specifying column select lines. SDRAM 1000 also includes a Y address operation
circuit 68 controlled by clock signal CLK for outputting signals YE0-YEk and signals YO0-YOk corresponding to selected column addresses as a peripheral circuit.
It should be noted that signals YE0-YEk represent internal column address signals corresponding to column addresses in memory cell array bank A0 or B0 and that signals YO0-YOk represent internal column address signals corresponding to column
addresses in memory cell array bank A1 or B1.
Although there are two banks in the above description, the number of banks can be increased and registers, buffers and I/O lines can be accordingly provided. In this example also, the banks can be accessed independently.
Data is written into memory cell array bank A0 or A1 according to the least significant bit of an address applied when a write command is input. Briefly describing the operation, when a write command is input, a Y decoder is activated according
to an applied address. The first data is stored into a register A0, and then the data stored in register A0 is written via I/O line GIO0 into memory cell array bank A0 in response to activation of signal .phi.WBA0.
The data received at the next rising edge of the clock signal is stored into register A1, and then written via I/O line GIO1 into memory cell array bank A1 in response to activation of signal .phi.WBA1. When writing the data of two bits is
completed, signals .phi.BA0 and .phi.BA1 are inactivated and the potential levels of I/O lines GIO0 and GIO1 connecting the memory cell arrays to the buffers are equalized for writing the next data.
SDRAM 1000 also includes an internal clock generation circuit 200 controlled in response to a signal .phi..sub.ACT generated for designating activating a circuit operation of an internal circuit and to chip select signal ext./CS for generating
internal clock signal int.CLK.
More specifically, internal clock generation circuit 200 is activated in response to activation of chip select signal ext./CS, and receives and is synchronized with external clock signal Ext.CLK and starts an operation for generating internal
clock signal int.CLK with a predetermined pulse width. Furthermore, internal clock signal generating circuit 200 stops the operation for generating internal clock signal int.CLK when signal .phi..sub.ACT is inactivated.
More specifically, every time some command is input to SDRAM 100 on standby, chip select signal ext./CS need be activated and responsively internal clock generation circuit 200 starts the operation for generating internal clock signal int.CLK.
On the contrary, when activating the SDRAM 1000 is designated, a data write operation or data read operation is completed and the internal circuit shifts to standby state, signal .phi..sub.ACT for designating activating the internal circuit attains
inactive low level. Responsively internal clock generation circuit 200 stops its operation. Thus, the circuit operation for generating internal clock signal int.CLK is stopped in SDRAM 1000 on standby and thus electricity consumption can be reduced.
FIG. 2 is a timing chart for illustrating a read operation of the SDRAM 1000 shown in FIG. 1.
FIG. 2 shows an example with a burst length of eight and a /CS latency of three.
At the rising edge of external clock signal Ext.CLK in cycle 1, a row address Xa is taken into SDRAM 1000 when chip select signal ext./CS and row address strobe signal ext./RAS each attain an active low level. Meanwhile, at the rising edge of
external clock signal Ext.CLK in cycle 1 when signal ext./RAS attains a low level and signals ext./CAS and ext./WE each attain a high level, a signal .phi..sub.ACTarray, i.e., the inverted version of a signal ZRASE-A for designating activating the
internal circuit, attains an active high level and signal .phi..sub.ACT is responsively activated for design | | |
