This invention relates to the structure of multiple registers used in image signal processing, and aims to simplify the register structure and to reduce the power consumption of the registers and the time required for testing an image signal processing LSI with the registers. A semiconductor integrated circuit according to the invention has a clock generation circuit and a clock buffer circuit for generating a plurality of clock signals, a register group including a plurality of registers connected in series and operable in synchronism with the clock signals, at least one combinational circuit connected to the register group, and means for selecting one of a normal operation mode and a scan test mode for the register group. The clock generation circuit receives a system clock CP.sub.IN, a scan test mode selection signal S.sub.MODEN, and clock CPS.sub.IN, and outputs a clock .phi. and a clock (.phi..sub.1 bar) controlled by the signal S.sub.MODEN such that the clocks have periods of "1" kept from overlapping each other, and also outputs a writing clock CPS used in the scan test mode. Since the register group is operated using the clocks, it is not necessary to form all registers of scan registers. As a result, the register group can be formed in a small area and made scannable. Moreover, the chip size and the power consumption can be further reduced by locating the clock buffer circuit adjacent to the register group.
The whole of a semiconductor integrated circuit operating in synchronism with a clock signal, is divided into a plurality of circuit blocks in units of a function, and different clock signals are supplied to the circuit blocks, respectively. Each of the circuit blocks is so constructed as to minimize the clock skew, by taking into consideration the size of clock buffers and the balance in load of the clock buffers. A data signal between two circuit blocks of the circuit blocks is transferred through a queue which is controlled to fetch the data in response to the clock signal supplied to the circuit block at the input side of the queue and to output the fetched data in response to the clock signal supplied to the circuit block at the output side of the queue.
The present generally relates to apparatus and methods for instrumentation associated with a downhole deployment valve or a separate instrumentation sub. In one aspect, a DDV in a casing string is closed in order to isolate an upper section of a wellbore from a lower section. Thereafter, a pressure differential above and below the closed valve is measured by downhole instrumentation to facilitate the opening of the valve. In another aspect, the instrumentation in the DDV includes sensors placed above and below a flapper portion of the valve. The pressure differential is communicated to the surface of the well for use in determining what amount of pressurization is needed in the upper portion to safely and effectively open the valve. Additionally, instrumentation associated with the DDV can include pressure, temperature, seismic, acoustic, and proximity sensors to facilitate the use of not only the DDV but also telemetry tools.
