Method and apparatus for testing semiconductor dice

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FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and more particularly to an improved method and apparatus for testing semiconductor dice including bare dice or dice encapsulated in chip scale packages.

BACKGROUND OF THE INVENTION

Recently, semiconductor dice have been supplied by manufacturers in an unpackaged or bare configuration. A known good die (KGD) is an unpackaged die that has been tested to a quality and reliability level equal to the packaged product. To certify a die as a known good die the unpackaged die must be burn-in tested. This has led to the development of test carriers that hold a single unpackaged die for burn-in and other tests. Each test carrier houses a die for testing and also provides the electrical interconnection between the die and external test circuitry. Exemplary test carriers are disclosed in U.S. Pat. Nos. 5,302,891; 5,408,190; 5,495,179 and 5,519,332 to Wood et al.

This type of test carrier includes external leads adapted to electrically connect to test circuitry via a burn-in board or other electrical receptacle. In addition, an interconnect component of the test carrier provides a temporary electrical connection between the bond pads on the die and external leads on the carrier. In the assembled carrier, a force distribution mechanism biases the device under test (DUT) against the interconnect.

One design consideration for this type of carrier is the electrical path between the carrier and the interconnect. Typically the carrier includes conductors in electrical communication with the external leads for the carrier. These conductors can be formed by plating, printing or depositing a highly conductive metal on a surface of the carrier. The interconnect also includes conductors in electrical communication with contact members that contact the bond pads on the die.

The electrical path between the conductors on the carrier and the conductors on the interconnect can be a wire bond or a mechanical electrical connection such as clips. It is desirable to minimize the length of this electrical path in order reduce parasitic induction and cross coupling of the test signals applied to the die. In addition, it is desirable that this electrical path be low resistance and reliable even with long term handling of the carrier in a production environment. For example, with an electrical path formed by wire bonds, the placement and integrity of the bond sites during their formation and continued usage can be a factor in the electrical performance of the carrier.

Another design consideration for this type of carrier is its suitability for use with different types of semiconductor dice and with the different types of interconnects needed to electrically connect to the dice. In general, semiconductor dice are fabricated in a variety of sizes and bond pad configurations. For example, conventional bare dice can have bond pads formed along their longitudinal edges (edge connect) or along their ends (end connect). On the other hand, a lead on chip (LOC) die can have bond pads formed along the center line of the die face. It would be desirable to have a carrier with a universal design able to accommodate the different types of semiconductor dice and the different types of interconnects required for electrical connection to the dice.

Furthermore, since the interconnects for a carrier are relatively expensive to manufacture, it would be desirable for the carrier to function with an interconnect that is as small as possible. Specifically, a peripheral outline of the interconnect should be just large enough to test a particular die configuration. This would help to keep the cost of the interconnects as low as possible, especially for silicon interconnects. However, as the size of the interconnects decreases the electrical connection with the interconnect becomes more difficult. Accordingly the carrier should also be constructed to make a reliable electrical connection with the interconnect regardless of size.

Other design considerations for a carrier include electrical performance over a wide temperature range, thermal management, power and signal distribution, the cost and reusability of the carrier, and the ability to remove and replace the interconnect. In addition, a carrier should be suitable for use with automated equipment and assembly procedures utilized in high volume semiconductor manufacture.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved method and apparatus for testing semiconductor dice are provided. The apparatus is in the form of a carrier comprising a base, an interconnect and a force applying mechanism. The base is adapted to retain a die and the interconnect and includes external leads connectable to external test circuitry associated with a burn-in board or other test apparatus.

The interconnect mounts to the base and includes contact members adapted to contact the die bond pads to establish temporary electrical communication with the die. The interconnect also includes conductive traces in electrical communication with the contact members. An electrical path is formed between the conductive traces on the interconnect and corresponding conductors on the base by wire bonding, tab bonding or slide clips. The force applying mechanism attaches to the base and is adapted to apply a biasing force to bias the die and interconnect together.

In a first embodiment of the carrier, the base includes a planar active surface for mounting the interconnect. The planar active surface includes a pattern of conductors. The interconnect mounts directly on top of the conductors with an insulating layer, such as a polymeric adhesive, placed therebetween. The conductors are formed in a universal pattern configured to accommodate different sizes of interconnects with a minimum length electrical path. For example, wire bonds can be formed between the conductors on the base and corresponding conductive traces on the interconnect. The universal pattern of conductors permits different sized interconnects to be easily interchangeable, and a reliable electrical connection to be made between the interconnect and base with reduced parasitic inductance.

In a second embodiment of the carrier, the base is formed with a stepped active surface rather than a planar active surface. The stepped active surface includes different support surfaces adapted to support interconnects having different sizes. Once again the conductors are formed over the stepped support surfaces in a universal pattern that permits wire bonds, or other electrical paths, to be formed between the base and interconnects with a minimum path length.

In a third embodiment of the carrier, an interposer is mounted to the base to provide a mounting surface for the interconnect and an electrical path to the interconnect. The interposer is an element that adapts the carrier for use with different types of interconnects for testing different types of semiconductor dice. In a first interposer embodiment, the interposer includes a pattern of conductors configured for connection to external test circuitry. The conductors in the interposer can be wire bonded, tab bonded or otherwise connected to conductors on the interconnect. In a second interposer embodiment, the interposer is an element that adapts a standard carrier for use with different interconnects suited for testing different types of semiconductor dice. In this embodiment the electrical path from external test circuitry is through the base and through the interposer to the interconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a carrier constructed in accordance with the invention;

FIG. 2 is a plan view of an interconnect for the carrier shown in FIG. 1;

FIG. 3 is a cross sectional view taken along section line 3--3 of FIG. 2;

FIG. 4 is a cross sectional view equivalent to FIG. 3 of an alternate embodiment interconnect having microbump contact members;

FIG. 5 is a perspective view of a base for the carrier of FIG. 1 having a planar active surface and pattern of conductors formed thereon;

FIG. 5A is a plan view of an alternate embodiment conductor pattern for the base shown in FIG. 5;

FIG. 6 is a perspective view of the planar active surface shown in FIG. 5 and the interconnect attached to the active surface;

FIG. 7 is a cross sectional view taken along section line 7--7 of FIG. 6;

FIG. 8 is a cross sectional view of an alternate embodiment stepped carrier base constructed in accordance with the invention and showing the interconnect mounted therein;

FIG. 9 is a cross sectional view of the alternate embodiment stepped base carrier shown in FIG. 8 but with another interconnect mounted therein;

FIG. 10 is a plan view taken along section line 10--10 of FIG. 8;

FIG. 11 is an exploded perspective view of an alternate embodiment carrier having an interposer for mounting the interconnect;

FIG. 12 is an enlarged perspective view of the interposer shown in FIG. 11 with a conductive path formed between the interposer and interconnect by wire bonding;

FIG. 12A is an enlarged perspective view of the interposer shown in FIG. 11 with a conductive path formed between the interposer and interconnect using TAB tape;

FIG. 13 is a perspective view of another alternate embodiment carrier having an interposer with a cavity for mounting the interconnect; and

FIG. 14 is a perspective view of another alternate embodiment carrier having an interposer with a flat surface for mounting the interconnect.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, a carrier 10 constructed in accordance with the invention is shown. The carrier 10 is adapted to establish temporary electrical communication with a semiconductor die 12 for testing or other purposes. In the illustrative embodiment the die 12 is a bare or unpackaged semiconductor die. A bare die does not include a conventional plastic or ceramic package. However, it is to be understood that the carrier 10 is also suitable for testing a chip scale semiconductor package. Chip scale semiconductor packages can include thin protective covers formed of glass or other materials bonded to the face and backside of a bare die.

The carrier 10 includes a carrier base 14, an interconnect 16 and a force applying mechanism 18. The interconnect 16 is adapted to establish temporary electrical communication with the die 12. The assembled carrier 10 is designed to be placed in a burn-in oven (not shown) or other test fixture for testing the die 12. The burn-in oven typically includes a socket or printed circuit board (PCB) in electrical communication with external test circuitry.

The force applying mechanism 18 secures the die 12 to the base 14 and presses the die 12 against the interconnect 16. The force applying mechanism 18 includes a pressure plate 20, a spring 22 and a bridge clamp 24. The force applying mechanism 18 also includes a latching mechanism in the form of clips 26, 28 on the bridge cla