A method and apparatus for transferring a block of pixel data from a source multi-line frame buffer area to a destination multi-line frame buffer area in a raster-type computer graphics display system. The method steps are performed by a state machine embedded in a macro function unit within a computer graphics subsystem: It is first determined whether the first raster line corresponding to the destination multi-line frame buffer area is at least a minimum number of raster lines ahead of the current raster line. If so, the state machine follows a fast path, during which the pixel data are transferred one line at a time from the source multi-line frame buffer area to the destination multi-line frame buffer area until the last line of pixel data in the block has been transferred. Then, the transfer operation stops. If not, then the state machine follows a slow path. In the slow path, the state machine times the line-by-line transfers of pixel data so as intentionally to remain behind the raster throughout the transfer operation: The state machine checks before each line is transferred to make certain that the destination line is behind the raster. But after each line is written, the state machine also checks to see whether the next destination line is ahead of the raster; this may occur if a vertical retrace has just begun. If so, the slow path procedure is interrupted, and the state machine switches to the fast path for the remainder of the transfer operation.

A method of self-programming a graphics processing unit (GPU) includes receiving a blit instruction defining a blit operation and storing a first control value in a control register, which determines the behavior of the GPU, using the blit operation. The blit instruction is read by the GPU from a command buffer asynchronously with the CPU. The blit operation is applied to a second control value to determine the first control value. The second control value can be stored in a memory, such as a second control register or a table of control values accessed by an index value. In one application, the second control value is a starting memory address for a display buffer, while in another application, second control value is a clip plane distance. The blit operation can include a copy operation, a colorkey operation, a logic operation, and/or a pattern copy operation on the first control value.

Improving a process in which information is read, modified, and written, and in which reading information is more costly (e.g., slower) than writing information. The information may be pixel information from a second (or remote) image and the modification may be a blending operation with a first (or local) image. The pixel information of the second (or remote) image may be stored in a video display frame buffer at a display adapter. The display adapter may be coupled via a bus, such as a PCI bus for example, with a CPU (or other machine) which performs the modification, such as image blending for example. This process is improved by limiting the number of reads of the pixel information of the second (or remote) image. Further, reads may be combined when doing so improves read performance and when alignment conditions are met. All modify and all or some write steps may be performed after all read steps have been performed, rather than performing all three (3) steps on a pixel-by-pixel, or pixel vector-by-pixel vector basis.

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.