This invention relates to a liquid crystal display device that reduces a parasitic capacitance, and a fabricating method thereof.A liquid crystal display device, including: a gate line with a multi-layer structure having a transparent first conductive layer and an opaque second conductive layer; a data line crossing the gate line with a gate insulating film in between to define a pixel area; a thin film transistor connected to the gate line and the data line; a pixel electrode formed of the first conductive layer in the pixel area, wherein the second conductive layer remains along an edge of the first conductive layer at an edge of the pixel area; a transmission hole that penetrates from an organic insulating film on the thin film transistor to the gate insulating film to expose the first conductive layer of the pixel electrode; a reflection electrode on the organic insulating film extending along a part of a side surface of the transmission hole to connect the pixel electrode and a drain electrode of the thin film transistor; and a floating electrode on the organic insulating film that overlaps both sides of the data line.

The present invention discloses a four-mask method of manufacturing an array substrate of a liquid crystal display device and the liquid crystal display device having the same array substrate. The method includes forming a plurality of gate lines, gate electrodes and gate extension lines by depositing a first metallic material on a substrate and patterning the first metallic material with a first mask, the gate extension lines extending toward the opposite direction of the gate electrodes; forming a first insulating layer on the whole surface having gate lines, gate electrodes, and gate extension lines; forming a plurality of data lines, source electrodes, drain electrodes, and capacitor electrodes over the gate lines by depositing a semiconductor layer, an ohmic contact layer and a second metallic material sequentially on the first insulating layer, and patterning the second metallic material and the ohmic contact layer with a second mask; forming a passivation layer and a plurality of first and second contact holes by depositing a second insulating layer on the data lines, the source electrodes, the drain electrodes and the capacitor electrodes, and patterning the second insulating layer with a third mask, the first contact holes exposing a portion of the drain electrode, the second contact holes exposing a portion of the capacitor electrodes; and forming a plurality of pixel electrodes by depositing a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer by a fourth mask, the pixel electrodes contacting the drain electrodes through the first contact holes and contacting the capacitor electrodes through the second contact holes.

The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.