Interconnect for making temporary electrical connections with bumped semiconductor components

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture, and more particularly to an improved interconnect for making temporary electrical connections with bumped semiconductor components such as wafers, dice and packages having contact bumps. Also provided are improved test systems and test methods that utilize the interconnect and methods for fabricating the interconnect.

BACKGROUND OF THE INVENTION

Various semiconductor components include contact bumps that provide connection points between the integrated circuits included in the component and the outside world. For example, bumped semiconductor wafers can include patterns of contact bumps. Singulated unpackaged dice, such as known good die (KGD), can also include contact bumps which permit the dice to be flip chip mounted in multi chip modules and other electronic systems. Other semiconductor components, such as packaged dice and chip scale packages, can also include contact bumps.

Typically, lead tin alloys (e.g., 95/5 lead tin alloy) and a ball limiting metallurgy (BLM) process are used to form the contact bumps. With this process the contact bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual areas of contact with contacts on a mating electrical component (e.g., circuit board). In addition, the contact bumps can be formed on the component in a dense array such as a ball grid array (BGA) . Micro ball grid arrays are formed in the smaller range, while standard ball grid arrays are formed in the larger size range.

With bumped semiconductor components, it is sometimes necessary to make non-bonded, or temporary, electrical connections with the contact bumps. For example, contact bumps can be used for probe testing of semiconductor wafers, or for burn-in testing bumped dice and packages. For testing unpackaged dice and chip scale packages, temporary packages can be used to house the dice or packages during the testing procedure.

In the past, following testing of semiconductor components having contact bumps, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step which adds to the expense and complexity of the testing process. Furthermore, the reflow process requires heating the tested components which can adversely affect the integrated circuitry contained in the component.

Another problem with making temporary electrical connection with contact bumps is that the sizes of the contact bumps can vary between different components, or within the same component. For example, typical contact bumps for a particular type of component can have diameters between 4.5 mils to 5.5 mils. In addition, the x-y location, and the planarity (i.e., z-direction location), of the contact bumps can also vary. These dimensional variations can cause misalignment making reliable temporary electrical connections difficult to form with the contact bumps.

Because of the increasing use of contact bumps in semiconductor manufacture, improved interconnects are needed for making temporary electrical connections to the contact bumps.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect for making temporary electrical connections with bumped semiconductor components is provided. The interconnect can be configured for use with semiconductor wafers, singulated semiconductor dice, or semiconductor packages. The interconnect is particularly suited for use in fabricating testing systems, and in performing testing procedures for bumped components.

The interconnect, generally stated, comprises: a substrate; contact members formed on the substrate for electrically contacting contact bumps on a semiconductor component; terminal contacts formed on the substrate for electrical connection to external electrical connectors of a testing apparatus; and conductors formed on the substrate for providing conductive paths between the contact members and terminal contacts.

The substrate can be formed of ceramic, silicon, FR-4, mullite, photosensitive glass, or photosensitive ceramic material. The contact members can be formed as recesses in the substrate covered with a conductive layer; as flat pads formed of a conductive material; as a conductive layer deposited on the substrate and etched with a recess; as raised projections etched into the substrate and covered with a conductive layer; or as textured microbumps on a multi layered tape similar to TAB tape.

In each contact member embodiment the conductive layers can be formed of a material that is non-reactive with the contact bumps. The contact members can also include a compliant layer for cushioning the contact forces applied by a testing apparatus to the interconnect. The terminal contacts can be formed as flat pads in a land grid array, as balls in a ball grid array, or as pins in a pin grid array. The conductors can comprise metal containing vias in the substrate or patterned metal layers on the substrate.

The interconnect can be included in a wafer level test system, or a die level test system. In the wafer level test system, the interconnect can be mounted to a probe card fixture of a conventional testing apparatus, such as a wafer handler. During a test procedure, test circuitry associated with the testing apparatus can apply test signals through the interconnect to the integrated circuits on the wafer. In addition, the test signals can be electronically switched as required, to selected dice on the wafer. In the die level test system, the interconnect can be mounted to a temporary package configured to house a single bare die or a chip scale package. The temporary package can be mounted to a testing apparatus such as a test socket or burn-in board configured to apply test signals through the interconnect to the die.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view of a bumped semiconductor die including contact bumps arranged in a ball grid array (BGA);

FIG. 1B is an enlarged cross sectional view of a contact bump taken along section line 1B--1B of FIG. 1A;

FIG. 1C is a graph illustrating a sampling of bumped semiconductor dice wherein an average minimum bump diameter (D.sub.MIN) and an average maximum bump diameter (D.sub.MAX) are ascertained;

FIG. 1D is a schematic cross sectional view of a chip scale package having contact bumps;

FIG. 1E is a schematic cross sectional view of another chip scale package