A numerically controlled oscillator (NCO) is defined to include counter circuitry and integrator circuitry. The counter circuitry includes a first input for receiving a minimum count value, a second input for receiving a maximum count value, and a third input for receiving an increment value. The counter circuitry is defined to generate a counter digital waveform that oscillates between the minimum count value and the maximum count value with a linear slope corresponding to the increment value. The integrator circuitry is defined to compute a running integral of the counter digital waveform. The running integral of the counter digital waveform represents a sinusoidal digital waveform output of the NCO.

A clock generator includes input circuitry for receiving an input signal and generating a memory address therefrom. A memory stores digital data indexed by the memory address which represents at least a portion of an analog clock. A digital to analog converter converts data retrieved from the memory to generate the analog clock which is then filtered by a filter and then converted into digital output clock.

A frequency synthesizer according to the direct digital synthesis method is provided. The frequency synthesizer includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored in its memory cells for the determination of sine-function values corresponding to phase values of the phase signal, a digital-to-analog converter for the conversion of time-discrete sine-function values into a quasi-analog sinusoidal time function and an anti-aliasing low-pass filter for smoothing the quasi-analog sinusoidal time function. The frequency synthesizer additionally contains an adder, which is connected between the memory unit and the digital-to-analog converter and which superimposes a non-periodic signal over the time-discrete sine-function values.

A digital-circuit return-to-zero device and method for digital-to-analog conversion is disclosed that uses an internal multiplexer alternatively selecting, or selecting in a scheduled fashion, digital input data and an expansion code. By the using the disclosed multiplexing process, where the expansion code is a null code, the usable analog spectrum of the digital-to-analog converter (DAC) extends beyond that of DACs. With the multiplexing process applied to a complementary interpolation process, the disclosed device is adapted for selective enhancement of the frequency spectrum proximate to the clock frequency. While extending the usable frequency spectrum beyond conventional DACs, the present invention, in its several embodiments, features low complexity and high portability relative to known response expansion solutions.

An apparatus for measuring jitter in a digital signal that includes an offset unit arranged to form an offset reference clock signal, being offset by a predetermined frequency amount from the digital signal. The apparatus also includes a sampler arranged to sample the digital signal at sampling times determined by the offset reference clock signal such that, in the absence of jitter and the offset by a predetermined frequency, there are a predetermined number of sampling times in each bit of the digital signal. The apparatus further includes at least one detector arranged to detect occasions when the number of sampling items in any bit of the digital signal is different from the predetermined number, and a counter arranged to count the occasions over a predetermined time. Also the apparatus includes an analyzer arranged to derive at least one measure of jitter from the counting of the occasions.