The temperature of the specimen holder 6 in the vacuum container 1 is lowered with the thermal control unit 11 to adjust the temperature of the specimen 7 composed of a silicon substrate to a low temperature of 0.degree. C. or lower. Then, trenches are formed in the specimen 7 by plasma etching using an etching gas comprising SF.sub.6 as the main constituent and optionally O.sub.2 as an additive. Thus, the etching rate and the yield can be increased in the trench formation in the silicon semiconductor substrate.

An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

The invention disclosed is an optical fiber which includes a central core glass region with a first refractive index profile. The fiber includes a second core glass region adjacent to and surrounding said central region, said second region having a thickness that varies along an axial direction of said second region and having a second refractive index profile that differs from said first profile. Additionally, the invention includes an optical fiber preform that can be drawn into the above fiber. The invention also includes the method of making the above describe optical fiber. Furthermore, the invention may also be practiced to make an optical fiber preform in accordance with the aforementioned invention. The aforementioned fiber and preform is particularly useful as a dispersion managed fiber or dispersion managed preform respectively.

Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. An ion gas comprising SF.sub.6 and N.sub.2 is directed at a target region in the back side. Using the ion gas, the target region in the back side is selectively etched using reactive ion etching (RIE) and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.