Circuit and method for testing an integrated circuit

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TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to integrated circuits and, in particular, to a circuit and method for testing an integrated circuit.

BACKGROUND OF THE INVENTION

An integrated circuit comprises a large number of semiconductor devices, such as transistors, that are fabricated on a semiconductor substrate. Integrated circuits are produced in quantity on fabrication lines. Before an integrated circuit is sold, the manufacturer tests the circuit for defects so that corrective action can be taken, if possible. To test the integrated circuit, the manufacturer applies test signals to selected pins of the integrated circuit. To speed up the process of testing large integrated circuits such as memory devices, the signals used to test the integrated circuit differ from the signals used in normal operation, even though the signals in both modes use the same pins of the integrated circuit. Therefore, designers have developed various techniques to differentiate test and normal modes of operation. Because this test mode should not be used once the chip successfully completes the tests, precautions must be taken to assure that the ultimate user of the circuit cannot inadvertently activate the test mode.

In a typical dynamic random access memory (DRAM) device, an out-of-specification voltage, typically 12 volts, is applied to one of the address pins to place the device into test mode for the manufacturer. Once in test mode, the manufacturer can test the operation of the memory device. By using an out-of-specification voltage to enter test mode, it is unlikely that an end user will place the device in test mode inadvertently. As the size of integrated circuits gets smaller, this technique becomes less reliable and the risk of damaging the circuit by shorting out components increases by exceeding the capacity of the circuit to pass current associated with the higher voltage.

In other memory devices, the test circuitry uses a latch circuit to determine when to enter test mode. These devices suffer from the problem that the ultimate user of the device could inadvertently initiate the test mode when turning on a computer that uses the device. Because it is not possible to disable the latch from entering the test state, the latch could be in the test state at power up thus allowing the ultimate user to activate the test circuitry.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a circuit and method for entering test mode that reduces the risk of damage to the device and reduces the chances that the ultimate user will inadvertently enter test mode.

SUMMARY OF THE INVENTION

The above mentioned problems with testing of integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A circuit and method for testing integrated circuits is described which enters test mode based on a control signal that maintains a logic value for a period of time that exceeds the specification for the control signal in the normal operation of the circuit. Advantageously, the circuit and method allow testing of the circuit with reduced risk of shorting out components of the circuit by using control signals with voltage levels that fall within the circuit's normal voltage levels and outside the normal timing of the signals. Further, the control signals used by the circuit and method to enter test mode also reduce the likelihood that test mode will be activated in normal operation by an end user due to differences in the timing of control signals between test mode and normal operation.

In particular, one illustrative embodiment of the present invention provides a selector circuit for placing a memory device in test mode. The selector circuit uses a logic circuit to determine when a control signal provided to a pin of the memory device maintains a first logic level for a period of time exceeding the specification for the control signal in normal operation. A multiplexer receives the control signal and a substitute control signal at an alternate pin of the memory device. The substitute control signal is used in place of the control signal during the test. The output of the logic circuit is coupled to control the multiplexer to select the control signal for use in addressing a cell of the memory device in normal operation and to select the substitute control signal for use in addressing a cell of the memory device in test mode.

In another embodiment, the logic circuit comprises a delay circuit coupled to receive and delay the control signal. Further, a logic gate receives the output of the delay and the control signal so as to produce an output signal that indicates when the control signal is in the first logic state for a period of time that exceeds the specification for normal operation of the memory device.

Another embodiment of the present invention includes a memory device that includes an enabling circuit coupled with the logic circuit to control the multiplexer. The enabling circuit receives at least one additional control signal that enables the selector to determine when to enter test mode.

In another embodiment, the enabling circuit further includes a feedback loop that locks out the effect of the enabling circuit once the selector circuit selects the test mode.

In another embodiment, the selector circuit receives the substitute control signal at an address pin that is not used to provide address information during a test in test mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an illustrative embodiment of the present invention;

FIG. 2 is a block diagram of an illustrative embodiment of a selector circuit for use in the embodiment of FIG. 1;

FIGS. 3A through 3E are timing diagrams illustrating the operation of the embodiment of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense.

FIG. 1 is a block diagram of an illustrative embodiment of the present invention. Memory device 10 includes selector circuit 12 that switches memory device between a normal operation mode and one or more test modes. Advantageously, selector circuit 12 responds to a signal that triggers the test mode of memory device 10 that does not risk shorting out components of memory device 10 despite the continued decrease in size of the components. Further, memory device 10 is designed such that in normal operation by an end user, memory device 10 will not inadvertently enter test mode.

Memory device 10 includes array of memory cells 14 constructed as known to a person of ordinary skill in the art. For example, memory device 10 may comprise a dynamic random access memory device (DRAM) or other appropriate integrated circuit. Addressing circuit 16 is coupled to array 14. Array 14 provides and receives data over input/output (I/O) lines 18. Further, address lines 20 are coupled to addressing circuit 16 to provide the address of a cell in array 14 to be accessed for reading or writing data. Control lines 22 are also coupled to addressing circuit 16 to provide signals for controlling the operation of memory device 10. Control lines 22, address lines 20 and input/output lines 18 include pins of memory device 10 that are coupled to electronic system 23.

Selector circuit 12 is coupled to receive a plurality of control signals from control lines 22 and address lines 20. In this embodiment, selector circuit 12 receives two row address strobe signals. The first row address strobe signal is the signal from electronic system 23, such as a processor based computer or other appropriate device. Alternatively, electronic system 23 may comprise a test circuit that provides signals to memory device 10 to test its operation. The first row address strobe is used in normal operation to latch in the row address for a cell to receive data from or provide data to electronic system 23. This signal is labeled "XRAS". Selector circuit 12 also receives a row address strobe signal for use in test mode that is labeled "TRAS". Selector circuit 12 is coupled to provide the appropriate row address strobe signal to addressing circuit 16 to be used to latch a row address in test and normal operation modes.

In operation, memory device 10 receives control signals at control lines 22 to operate in either normal operation mode or in one or more test modes. Selector circuit 12 selects between TRAS for test mode and XRAS for normal operation based on at least one control signal, including XRAS, from control lines 22. For example, selector circuit 12 places memory device 10 in test mode when XRAS transitions to a low logic level and maintains the low logic level for a period of time that exceeds the specification for XRAS in the normal operation mode. For example, selector circuit 12 can place memory device 10 in test mode when XRAS provides a low logic value for at least 1 millisecond or other appropriate time period based on the manufacturers specification for the row address strobe signal.

As a further precaution to prevent an end user from inadvertently entering test mode, selector circuit 12 can base the decision on the state of additional control signals. In the embodiment of FIG. 1, selector circuit 12 uses write enable (WE) and column address strobe (CAS) to determine whether memory device 10 is in test mode. For example, selector circuit 12 can pass TRAS when write enable and column address strobe signals change to low logic values before XRAS goes low. Once in test mode, signals are applied to control lines 22, address lines 20 and input/output lines 18 to test the cells of array 14 using conventional test schemes as known to a person of ordinary skill in the art. The signal used for TRAS is applied to an unused address pin. Alternatively, TRAS can be provided to another appropriate pin of memory device 10 such as a pin not used in the normal operation of memory device 10.

FIG. 2 is a block diagram of an illustrative embodiment of a selector circuit 12a for use in memory device 10 of FIG. 1. Selector circuit 12a includes a multiplexer 24 that is coupled to receive the two row address strobe signals, TRAS and XRAS. A selector input of multiplexer 24 is controlled by logic circuit 26 and enabling circuit 28 through AND-gate 30 and OR-gate 32. Specifically, enable circuit 28 is coupled to receive three control signals, namely, XRAS, CAS, and WE. Enable circuit 28 produces a signal, labeled WCBR, and provides this signal to a first input of OR-gate 32. Logic circuit 26 is coupled to receive XRAS as an input and to provide an output to a f