A fast CORDIC algorithm and the resulting VLSI architecture for the evaluation of trigonometric functions are disclosed. The new method employs signed digits to represent intermediate operands and requires a constant scaling or normalization factor which can be pre-computed and made available in read-only hardware for any desired target precision (i.e., word length). The speedup is achieved by performing CORDIC iterations in parallel in two separate modules. Each module executes a "double step" or two basic CORDIC rotations at every iteration cycle. Two angles arctan 2.sup.-2i and arctan 2.sup.-(2i+1) are used in each step i of the method. As a result, approximately n/2 steps (exactly ##EQU1## steps) are required to evaluate sine/cosine of n bit input argument up to n bits of accuracy. The VLSI architecture consists of two "zeroing" and two "rotator" modules, each consisting of signed digit adders, latches, shifters, etc. A novel decision block controls the iterations. The new ROM look-up table stores ##EQU2## values, each accurate to n+3 bits. For every pair of consecutive angles arctan 2.sup.-2i and arctan 2.sup.-(2i+1) for i=0, 1, 2, . . . , ##EQU3## only their sum and difference need be stored for the inventive double step branching CORDIC method. The result is a very fast VLSI architecture whose speedup to hardware-overhead ratio is close to 1. The double stepping method can be easily extended to the evaluation of inverse trigonometric, exponential as well as logarithm functions.

A circuit for digitally generating a series of encoded sampling values of a periodic function by virtue of ROM table conversion, include (a) a function ROM in which an amplitude associated with one-fourth of a period of a periodic function is stored, and (b) an address counter which generates an address signal to be input into the function ROM. The address counter includes an accumulator, a first register which is externally controllable, an adder which adds an output transmitted from the accumulator to an output transmitted from the first register, and transmits the sum to the accumulator, an address-conversion circuit receives a first output transmitted from the adder, and converts the first output into the address signal, the first output being a bit output other than a second uppermost bit output among bit outputs transmitted from the adder, a second register which stores therein an output transmitted from the address-conversion circuit, and a zero-cross flag control circuit which receives an uppermost bit output transmitted from the accumulator, and makes logic control. An output transmitted from the second register is input into the function ROM as the address signal. The function ROM has the (2.sup.P +1) number of address regions where P indicates the number of bits other than a second uppermost bit output among outputs transmitted from the adder. The series of encoded sampling values is defined as a sum of an output transmitted from the function ROM and an output transmitted from the zero-cross flag control circuit.