A combinational logic feedback circuit ensures correct power-on-reset of a 4-bit synchronous shift register used to generate a plurality of page select signals. The combinational circuit monitors the plurality of page select signals and asserts an invalidity signal when an invalid state is detected. A deglitch circuit inhibits or suppresses glitches which may be output from the combinational circuit due to state transitions of one or more of the page select signals. The deglitch circuit generates in response thereto a reset signal which is applied to the synchronous shift register to reset the shift register to output a valid state.
A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a "de-glitching" time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.
