Synchronous clock generator including a false lock detector

Claims

What is claimed is:

1. A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal, comprising:

a delay line included in said locked loop, said delay line producing a signal at a 90.degree. tap thereof; and

a logic circuit including a flip-flop connected to receive the signal from the 90.degree. tap and the clock signal, said logic circuit for determining if a predetermined phase relationship exists between the signal from the 90.degree. tap and the clock signal and for producing an output signal indicative of said determination.

2. A false lock detector for use with a delay-locked loop which produces a plurality of output signals in response to a clock signal, comprising:

a delay line included in said delay-locked loop, said delay line producing a signal at a 90.degree. tap thereof; and

a logic circuit connected to receive first and second signals produced by the delay-locked loop, said logic circuit including a flip-flop connected to receive the signal from the 90.degree. tap and the clock signal, said signal from the 90.degree. tap having known states when said clock signal changes states, said logic circuit producing an output signal indicative of whether said signal from the 90.degree. tap is in said known states when said clock signal changes states.

3. A delay-locked loop having a false lock detector, comprising:

a delay line for receiving a clock signal and for producing a plurality of output signals each having a predetermined delay with respect to the clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

4. The delay-locked loop of claim 3 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

5. A synchronous clock generator having a false lock detector, comprising:

a receiver for receiving an external clock signal;

a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line;

a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

6. The synchronous clock generator of claim 5 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

7. A system, comprising:

a processor;

a memory controller;

a plurality of memory devices,

a first bus interconnecting said processor and said memory controller; and

a second bus interconnecting said memory controller and said memory devices;

each of said memory devices having a synchronous clock generator, comprising:

a receiver for receiving an external clock signal;

a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line;

a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

8. An internal clock generator circuit, comprising:

a clock generator including a locked loop constructed to provide first and second internal clock signals, the first clock signal having a phase determined by first and second phase control signals applied to respective first and second control inputs of the clock generator;

a phase detector coupled to the clock generator to receive the first internal clock signal, the phase detector further receiving a reference clock signal, the phase detector being constructed to generate an output signal indicative of the phase of the first internal clock signal relative to the phase of the reference clock signal, the output signal being coupled to the first control input of the clock generator; and

a false lock detector coupled to the clock generator to receive the second internal clock signal and another clock signal coupled to or from the clock generator, the false lock detector generating a false lock signal responsive to a predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal, the false lock signal being applied to the second control input of the clock generator to alter the phase of the first internal clock signal.

9. The internal clock generator circuit of claim 8 wherein the other clock signal comprises a clock signal generated by the locked loop.

10. The internal clock generator circuit of claim 8 wherein the predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal comprises 90 degrees.

11. A delay locked loop, comprising:

a delay line receiving a reference clock signal and generating first and second delayed clock signals, the first delayed clock signal having a phase relative to the phase of the reference clock signal that is determined by a signal applied to a control terminal of the delay line;

a phase detector coupled to the delay line to receive the first delayed clock signal and coupled to receive the reference clock signal, the phase detector generating a signal at an output terminal indicative of the phase of the first delayed clock signal relative to the phase of the reference clock signal, the output terminal of the phase detector being coupled to the control terminal of the delay line; and

a false lock detector coupled to the delay line to receive the second delayed clock signal, the false lock detector being constructed to apply a signal to the control terminal of the delay line responsive to a predetermined characteristic of the second delayed clock signal indicative of a false lock condition of the delay locked loop.

12. The delay locked loop of claim 11 wherein the predetermined characteristic comprises the logic level of the second delayed clock signal at a transition of the first delayed clock signal.

13. The delay locked loop of claim 11 wherein the predetermined characteristic comprises the phase of the second delayed clock signal relative to the phase of the first delayed delayed clock signal.

14. A method of generating an internal clock signal, comprising:

adjusting the phase of the internal clock signal relative to a reference clock signal using a locked loop, the locked loop adjusting the phase of the internal clock signal as a function of the phase relationship between the internal clock signal and the reference clock signal in an attempt to maintain a predetermined phase relationship between the internal clock signal and the reference clock signal;

detecting a false lock condition of the locked-loop using at least one clock signal generated by the locked loop and another clock signal coupled to or from the locked loop; and

altering the phase of the internal clock signal in a single direction responsive to detecting the false lock condition.

15. The method of claim 14 wherein the false lock condition is detected using clock signals from the locked loop having respective phases that differ from each other by approximately 90 degrees.

16. The method of claim 14 wherein the false lock condition is detected by examining the logic level of the at least one clock signal generated by the locked loop at a transition of the other clock signal coupled to or from the locked loop.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed generally to the field of integrated circuits and, more particularly, to the generation of clock signals for controlling the operation of such circuits.

2. Description of the Background

Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc. rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and SLD-RAM require individual parts to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important.

Typically, operations are initiated at the edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge.

One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90.degree., 180.degree. and 270.degree., respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations.

An example of such an approach is shown in FIG. 1 where the timing of operations in a memory device 10 is defined by an externally provided control clock reference signal CCLKREF and an externally provided data clock reference signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in a memory controller 11 and transmitted to the memory device 10 over a control clock bus 13 and a data clock bus 14, respectively. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the control clock reference signal CCLKREF is a continuous signal and the data clock reference signal DCLKREF is a discontinuous signal, i.e., the data clock reference signal DCLKREF does not include a pulse for every clock period. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time upon arrival at the memory device 10 due to differences in propagation times, such as may be produced by routing differences between the control clock bus 13 and the data clock bus 14.

Control data CD1-CDN arrive at respective input terminals 16 substantially simultaneously with pulses of the control clock reference signal CCLKREF and are latched in respective control data latches 18. However, if the device attempts to latch the control data CD1-CDN immediately upon the edge of the control clock reference signal CCLKREF, the control data may not have sufficient time to develop at the input terminals 16. For example, a voltage corresponding to a first logic state (e.g., a "0") at one of the input terminals 16 may not change to a voltage corresponding to an opposite logic state (e.g., a "1") by the time the data are latched. To allow time for the control data CD1-CDN to fully develop at the input terminals 16, the control data are latched at a delayed time relative to the control clock reference signal CCLKREF. To provide a clock edge to trigger latching of the control data CD1-CDN at the delayed time, a delay circuit 20 delays the control clock reference signal CCLKREF by a delay time to produce a first delayed clock signal CCLKD. Edges of the first delayed clock signal CCLKD activate the control data latches 18 to latch the control data CD1-CDN.

Data DA1-DAM arrive at data terminals 22 substantially simultaneously with the data clock reference signal DCLKREF. Respective data latches 24 latch the data DA1-DAM. As with the control data CD1-CDN, it is desirable that the data DA1-DAM be latched with a slight delay relative to transitions of the data clock reference signal DCKLREF to allow time for signal development at the data terminals 22. To provide a delayed clock edge, a delay circuit 26 delays the data clock reference signal DCLKREF to produce a phase-delayed data clock DCLKD that is delayed relative to the data clock reference signal DCLKREF.

For latching both control data CD1-CDN and data DA1-DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clocks CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data, respectively. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CD1-CDN or data DA1-DAM relative to the clock signals CCLKREF, DCLKREF, respectively, of the memory device 10.

One possible approach to producing a variable delay is for the control clock generator to employ a delay-locked loop 28 driven by the external reference clock CLKREF, as shown in FIG. 2. The control clock reference signal CLKREF is input to a conventional, multiple output, variable delay line 30 such as that described in Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits 31(11):1723-1732, November 1996. The delay line 30 is a known circuit that outputs multiple delayed signals CLK1-CLKN with increasing lags relative to the reference signal CLKREF. The delays of the signals CLK1-CLKN are variably responsive to a control signal Vcon received at a control port 32.

A feedback path, formed by a comparator 34 and an integrator 36, produces the control signal Vcon. The feedback path receives the control clock reference signal CCLKREF at one input of the comparator 34 and receives one of the output signals CLKN from the delay line 30 as a feedback signal at the other input of the comparator 34. The comparator 34 outputs a compare signal Vcomp that is integrated by the integrator 36 to produce the control signal Vcon.

As is known, the control signal Vcon will depend upon the relative phases of the control clock reference signal CCLKREF and the feedback signal CLKN. If the feedback signal CLKN leads the control clock reference signal CCLKREF, the control signal Vcon increases the delay of the delay line 30, thereby reducing the magnitude of the control signal Vcon until the feedback signal CLKN is in phase with the control clock reference signal CCLKREF. Similarly, if the feedback signal CLK lags the control clock reference signal CCLKREF, the control signal Vcon causes the delay line 30 to decrease the delay until the feedback signal CLKN is in phase with the control clock reference signal CCLKREF.

A delay-locked loop may obtain a "false lock". In the case of a delay-locked loop, the voltage-control delay line may store multiples of the desired interval even though the output-to-input phase relationship would look identical to the desired relationship. For example, the desired storage (delay) may be 180.degree., but the actual storage (delay) may be 540.degree.. That could cause a problem if the delay line were used to create local clocks, because the tap-to-tap spacing would be three times the desired spacing.

It is possible to address the issue of false lock by comparing the control voltage to an expected value of the control voltage to determine if the actual value is likely to be causing an extraordinarily long delay. However, comparison of the control voltage to an expected value of the control voltage is generally impractical because process variations, temperature, and supply voltage variation