The present invention relates to a programmable retargeter memory device which receives data being sent to addresses designated by the data and which retargets the data by replacing the addresses designated by the data with new addresses. The retargeter memory device of the present invention comprises an address memory and a data memory. The address memory comprises a plurality of address memory locations for storing retargeted addresses. The address memory is capable of being written to and read from to programmably alter the retargeted addresses stored therein and to output retargeted addresses therefrom. The data memory comprises a plurality of data memory locations for storing data associated with the retargeted addresses stored in the address memory and is capable of being written to and read from. Each data memory location is associated with one address memory location such that a write to a particular data memory location causes the retargeted address stored in the address memory location associated with the particular data memory location to be released from the address memory and sent to the location designated by the released retargeted address followed by the data written to the particular data memory location. The programmable retargeter memory device of the present invention can be provided with a release and re-order function which allows the data received by the programmable retargeter memory device of the present invention to be re-ordered before being sent to the retargeted addresses downstream.
Processes are monitored as components are loaded into memory. Relocation of a component to an alternate base address instead of its preferred base address, causes an alternate component to be created corresponding to the relocated component. The alternate component is a copy of the relocated component, but the preferred base address of the alternate component is reset to be the alternate base address of the relocated component. Additional alternate components may be created for each relocated component, with each additional alternate component being optimized in a different manner. Alternate components may be implemented as alternate data stream of the corresponding relocated components. In response to subsequent requests to load a selected component into memory, it is determined whether the selected component has at least one corresponding alternate component. If so, one of the corresponding alternate components is loaded into memory instead of the selected component.
Processes are monitored as components are loaded into memory. Relocation of a component to an alternate base address instead of its preferred base address, causes an alternate component to be created corresponding to the relocated component. The alternate component is a copy of the relocated component, but the preferred base address of the alternate component is reset to be the alternate base address of the relocated component. Additional alternate components may be created for each relocated component, with each additional alternate component being optimized in a different manner. Alternate components may be implemented as alternate data stream of the corresponding relocated components. In response to subsequent requests to load a selected component into memory, it is determined whether the selected component has at least one corresponding alternate component. If so, one of the corresponding alternate components is loaded into memory instead of the selected component.
A graphics request stream is transferred from a host processor to a graphics card via a host bus so that the stream traverses the host bus no more than once. To that end, the graphics card has a graphics card memory, and the host processor has a host memory configured in a first memory configuration. The graphics card memory may be configured in the first memory configuration, and the graphics request stream is received directly in a message from the host processor (via the host bus). Upon receipt by the graphics card, the graphics request stream is written to the graphics card memory.
Processes are monitored to determine if all of their components are loaded from persistent storage into memory at their preferred base addresses. Each of the components is examined to determine if that component's in-memory base address matches the preferred base address of its on-disk representation. If a base address collision is detected, the on-disk representation of the preferred base address is updated to reflect the new in-memory base address.
