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Claims  |
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I claim:
1. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions;
a main control block arranged at least in the central region of the 9 regions, the main control block including a first pad group; and
memory blocks arranged respectively in the 8 peripheral regions of the 9 regions and controlled by the main control block, each of the memory blocks including a second pad group.
2. A semiconductor memory device according to claim 1, further comprising:
a package having external terminals dispersed on a surface in a two-dimensional manner, wherein the external terminals of the package are connected to the first and second pad groups.
3. A semiconductor memory device comprising:
a semiconductor chip divided into a plurality of memory blocks; and
input/output pads receiving an input data and an output data and power supply pads receiving an external power-source potential for data input/output operations, the input/output pads and power supply pads arranged, respectively, in the plurality
of memory blocks.
4. A semiconductor memory device according to claim 3, wherein the semiconductor chip is divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions, a main control block is
arranged at least in the central region of the 9 regions and memory blocks controlled by the main control block are arranged respectively in the 8 peripheral regions of the 9 regions, each of the plurality memory blocks including a memory cell array, a
data input/output circuit and a memory control circuit.
5. A method of laying out a semiconductor memory device comprising steps of:
preparing 8 circuit patterns for 8 memory blocks, each of the memory blocks including a memory cell array, a data input/output circuit, and a memory control circuit and preparing a circuit pattern for a main control block for controlling the
memory block; and
arranging 9 regions in a 3.times.3 pattern, the main control block being located in a central region of the 9 regions and the 8 memory blocks being located in eight peripheral regions surrounding the central region, each region having a same
size.
6. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions;
a main control block arranged at least in the central region of the 9 regions for receiving an external address signal, an external command signal, an external clock signal, and an external power supply potential and for sending out an internal
address signal, an internal command signal, an internal clock signal, and an internal power supply potential; and
memory blocks arranged, respectively, in the 8 peripheral regions of the 9 regions and controlled by the main control block, each of the plurality of memory blocks for receiving the internal address signal, the internal command signal, the
internal clock signal, the internal power supply potential, and an input data from an external element and for sending out an output data to the external element.
7. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern including one central region and 8 peripheral regions;
a main control block arranged at least in the central region of said 9 regions for receiving an external address signal, an external command signal, an external clock signal, and an external power supply potential and for sending out an internal
address signal, an internal command signal, an internal clock signal, and an internal power supply potential;
memory blocks arranged, respectively, in the 8 peripheral regions of the 9 regions and controlled by the main control block, each of the plurality of memory blocks for receiving the internal address signal, the internal command signal, the
internal clock signal, the internal power supply potential, and an input data from an external element and for sending out an output data to the external element;
a first external pad group arranged in the main control block for receiving the external address signal, the external command signal, the external clock signal, and the external power supply potential;
a second external pad group arranged in each of the plurality of memory blocks for receiving the input data and the output data;
supply wires connecting the main control block and each of the plurality of memory blocks for supplying each of the plurality of memory blocks with the internal address signal, the internal command signal, the internal clock signal, and the
internal power supply potential generated by the main control block; and
data transfer circuits arranged in the 8 memory blocks, each connecting the corresponding second external pad group arranged in each of the plurality the memory blocks and a memory cell array arranged in said each of the plurality of the memory
blocks, each data transfer circuit being arranged in a layer that is disposed lower than a layer having the supply wires.
8. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions;
a logic integrated circuit arranged in the central region of said 9 regions, and including a pad group; and
memory integrated circuits arranged, respectively, in the 8 peripheral regions of said 9 regions except the central region, each of the memory integrated circuits including a pad group.
9. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions;
memory integrated circuits arranged, respectively, in the 8 peripheral regions of the 9 regions except the central region, each of the memory integrated circuits including a memory cell array, an I/O buffer for inputting an input data from an
external element and outputting an output data to the external element, a data transfer system circuit for transferring the input data from the I/O buffer to the memory cell array and the output data from the memory cell array to the I/O buffer, an I/O
control circuit for controlling the I/O buffer, and a memory control circuit for controlling the data transfer system circuit; and
a circuit arranged in the central region of the 9 regions and including an address generator for simultaneously addressing the memory cell arrays included in the 8 memory integrated circuits and a command generator also arranged in the central
region for simultaneously specifying an operation mode to the I/O and memory control circuits included, respectively, in the 8 memory integrated circuits.
10. A semiconductor memory device comprising:
a semiconductor chip divided into 9 regions having an equal area in a 3.times.3 pattern and including one central region and 8 peripheral regions;
memory integrated circuits arranged respectively in the 8 peripheral regions of the 9 regions except the central region; and
a logic integrated circuit arranged in the central region of the 9 regions;
each of the 8 peripheral regions of the 9 regions being further divided into first, second and third sub-regions, the first and second sub-regions having a same contour with the third sub-region arranged therebetween, a memory cell array being
arranged in each of the first and second sub-regions, a data input/output circuit for sending out the output data from the memory cell array to an external element of the semiconductor chip and inputting input data from the external element of the
semiconductor chip into the memory cell array and a control circuit for controlling the operation of the data input/output circuit being arranged in the third sub-region;
a circuit for simultaneously addressing the memory cell arrays included in the 8 memory integrated circuits and a circuit for simultaneously specifying an operation mode to at least the control circuits included respectively in the 8 memory
integrated circuits being arranged in the central region of the 9 regions.
11. A semiconductor memory device according to claim 1, wherein the main control block includes a main control circuit connected to the first pad group, and each of the memory blocks includes a local control circuit connected to the main control
circuit, the second pad group, and a memory cell array which is connected to the local control circuit.
12. A semiconductor memory device according to claim 11, wherein the local control circuit includes a memory control circuit and a data input/output circuit connected to the second pad group and the memory cell array.
13. A semiconductor memory device according to claim 12, wherein the data input/output circuit includes an I/O control circuit and an I/O buffer which is connected to the second pad group and the memory cell array via a data transfer system
circuit connected to the memory control circuit.
14. A semiconductor memory device according to claim 13, wherein the data transfer system circuit includes a bit line sense amplifier/bit line equalizer, a column gate, and a data line circuit.
15. A semiconductor memory device according to claim 1, wherein the first pad group includes an address signal pad group, a command signal pad group, a clock signal pad, and a first power source pad group and the second pad group includes an I/O
pad group and a second power source pad group.
16. A semiconductor memory device according to claim 15, wherein the main control block includes an address generator receiving an address signal, a command generator receiving a command signal, a clock generator receiving a clock signal, and a
DC voltage generator receiving an external power-source potential and each of the memory blocks includes a data input/output circuit receiving an input data, an output data, and an external power-source potential.
17. A semiconductor memory device according to claim 2, wherein the package has a connection substrate and the semiconductor chip is a flip-chip connection type.
18. A semiconductor memory device according to claim 17, wherein the connection substrate is a ball grid array type.
19. A semiconductor memory device according to claim 18, wherein the connection substrate is a pin grid array type.
20. A semiconductor memory device according to claim 6, wherein each of the memory blocks includes a memory cell array, an I/O buffer, a data transfer system circuit connected to the memory cell array and the I/O buffer, a memory control circuit
for controlling the data transfer system circuit in accordance with the internal address signal, the internal command signal, and the internal clock signal, and an I/O control circuit for controlling the I/O buffer in accordance with the internal command
signal and the internal clock signal.
21. A semiconductor memory device according to claim 20, wherein the data transfer system circuit includes a bit line sense amplifier/bit line equalizer, a column gate, and a data line circuit.
22. A semiconductor memory device according to claim 21, wherein the memory control circuit includes a row decoder for selecting a row of the memory cell array in accordance with the internal address signal, a bit line control circuit for
controlling the bit line sense amplifier/bit line equalizer in accordance with the internal command signal and the internal clock signal, a column decoder for selecting the column gate in accordance with the internal address signal, and a data line
control circuit for controlling the data line circuit in accordance with the internal command signal and the internal clock signal.
23. A semiconductor memory device according to claim 22, further comprising:
a data line group including a bit line connected to the memory cell and the column gate via the bit line sense amplifier/bit line equalizer, a DQ line connected to the column gate and the data line circuit, and a final data line connected to the
data line circuit and the I/O buffer.
24. A semiconductor memory device according to claim 23, wherein the data line group is disposed in each of the 8 peripheral regions.
25. A semiconductor memory device according to claim 22, further comprising a wiring group including an internal signal line connected to the main control block and each of the memory blocks and an internal clock signal line connected to the
main control block and each of the memory blocks.
26. A semiconductor memory device according to claim 25, wherein the wiring group is disposed between two adjacent regions of the 9 regions.
27. A semiconductor memory device according to claim 22, further comprising an internal address signal line group connected to the main control block and each of the memory blocks.
28. A semiconductor memory device according to claim 27, wherein the internal address signal line group is disposed between two adjacent regions of the 9 regions.
29. A semiconductor memory device according to claim 22, further comprising a bit line control signal line group connected to the bit line control circuit and the bit line sense amplifier/bit line equalizer.
30. A semiconductor memory device according to claim 29, wherein the bit line control signal line group is disposed in each of the 8 peripheral regions.
31. A semiconductor memory device according to claim 22, further comprising an I/O control signal line group connected to the I/O control circuit and the I/O buffer.
32. A semiconductor memory device according to claim 31, wherein the I/O control signal line group is disposed in each of the 8 peripheral regions.
33. A semiconductor memory device according to claim 6, wherein each of the memory blocks includes first and second memory cell arrays, first and second I/O buffers, and first and second data transfer system circuits, the first data transfer
system circuit being connected to the first memory cell array and the first I/O buffer, the second data transfer system circuit being connected to the second memory cell array and the second I/O buffer.
34. A semiconductor memory device according to claim 33, wherein the first data transfer system circuit includes a first column gate and a first data line circuit, and the second data transfer system circuit includes a second column gate and a
second data line circuit.
35. A semiconductor memory device according to claim 34, further comprising:
a first data line group including first bit lines connected to the first memory cell and the first column gate, first DQ lines connected to the first column gate and the first data line circuit, and first final data lines connected to the first
data line circuit and the first I/O buffer; and
a second data line group including second bit lines connected to the second memory cell and the second column gate, second DQ lines connected to the second column gate and the second data line circuit, and second final data lines connected to the
second data line circuit and the second I/O buffer.
36. A semiconductor memory device according to claim 35, wherein the first DQ lines are multiplexed by the first final data lines by using the internal address signal of the first data line circuit and the second DQ lines are multiplexed by the
second final data lines by using the internal address signal of the second data line circuit.
37. A semiconductor memory device according to claim 35, wherein the first and second data line circuits are, respectively, linked and the first and second DQ lines are multiplexed by the first and second final data lines by using the internal
address signal of the first and second data line circuits linked to each other. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention generally relates to a semiconductor memory device and, more particularly, relates to a structure and method of arranging and wiring memory blocks and external pads that can realize a fast flow of data.
FIGS. 29A and 29B of the accompanying drawings show a background dynamic type RAM. FIG. 29A is an external plan view whereas FIG. 29B is a plan view showing an inside of a package.
As shown in FIG. 29A, a dynamic type RAM (hereinafter referred to as a DRAM) type chip 100 is rectangularly parallelepipedic with short and long edges having a ratio of about 1:2. A group of pads 102 operate as input/output terminals of the chip
100. Two pad group arrangements are currently popular. The pad group 102 may be arranged either along an edge of the chip 100 or longitudinally along a central line of the short edges, the latter being referred to as a center pad arrangement.
As shown in FIG. 29B, with a chip 100 having a center pad arrangement, the pad group 102 of the chip 100 and the lead group of a package 200 are connected to each other by a bonding wire 300 when the chip 100 is housed in a resin-sealed package
200. Then, the DRAM can be provided with external input/output terminals on lateral sides of the package 200 along the longitudinal direction thereof.
Currently, efforts are being made to provide improved or newly developed DRAMs having a large memory capacity and enhanced functional features.
Enhanced functional features may be expressed in terms of bits. Multi-bit products include 4-bit, 8-bit, 16-bit and 32-bit DRAMs. The number of data input/output pads dramatically increases for multi-bit DRAMs of a higher order. This means
that, with the center pad arrangement illustrated in FIGS. 29A and 29B, a chip 100 may not be able to accommodate a large number of pads.
Additionally, as a memory capacity is increased for DRAMs, more and more fine and minute circuit elements including memory cells and transistors are used. However, the efforts for producing fine and minute circuit elements can not necessarily
catch up to the increased degree of integration of a DRAM, particularly in terms of a number of circuit elements so that a large chip 100 is inevitably used for each product. A large chip 100 means long wires used in a data transfer circuit to connect
I/O pads and memory cells for storing data of a DRAM, and long control signal lines extending from a control circuit for controlling the data transfer circuit to the data transfer circuit itself. Long control signal lines and long wires used in the data
transfer circuit by turn give rise to a problem of requiring a large space for accommodating the wires and a problem of a slow transmission rate for control signals and data signals.
FIG. 30 is a plan view of a background DRAM showing an arrangement of data lines.
As shown in FIG. 30, data lines include bit lines (BL) formed in memory cell arrays 104, DQ lines (DQ) arranged perpendicularly relative to the respective bit lines in sense amplifier regions 106 and connected to the bit lines by way of
respective column gates (not shown), RWD lines (RWD) formed in bus regions 108 along center lines of 16M core blocks in parallel with the bit lines BL and connected to the DQ lines by way of respective DQ buffers (not shown) and RD/WD lines (RD/WD)
formed in peripheral region 110 and connecting the RWD lines and I/O buffers formed in the peripheral region 110.
Currently, the peripheral region 110 is produced by separating four 16M core blocks from one another and the peripheral region 110 has a cross-like plan view. A control circuit (CNT.), internal power supply generating circuits (VPP, VREF, SSB),
an address buffer and an I/O buffer are arranged within the cross-shaped peripheral region 110. More specifically, referring to FIG. 30, the control circuit is arranged at the crossing and the internal power supply generating circuits are arranged in
the upper and lower regions of the shorter bar-like section of the peripheral region 110 separating the 16M core blocks, while the address buffer and the I/O buffer are arranged respectively in the right and left regions of the longer bar-like section of
the peripheral region 110 separating the 16M core blocks.
Note that R/D stands for a row decoder and C/D stands for a column decoder in FIGS. 29A and 30.
With the data line arrangement of FIG. 30, the longest data line connecting a memory cell and the I/O buffer is about as long as the longer edge of the chip 100.
In the field of semiconductor memory devices including DRAMs, multi-bit devices are inevitably accompanied with a large chip size. Multi-bit devices of a higher order involve a large number of pads and a large chip size involves long control
signal lines and long data lines. While these problems may be currently negligible, they will become serious in the future with the trend of seeking multi-bit devices of an even higher order. For instance, a large number of pads will pose a problem of
the difficulty with which they are appropriately arranged. Long control signals lines and data lines will make it difficult to maintain the throughput of a semiconductor memory device to a desired level.
BRIEF SUMMARY OF THE INVENTION
In view of the above identified problems and other problems, it is therefore an object of the present invention to provide a novel semiconductor memory device adapted to enhanced functional features and a large memory capacity as well as a method
of laying out such a semiconductor memory device, a method of driving such a memory device and a circuit arrangement pattern suitable for such a memory device.
According to the present invention, the above object is achieved by providing a novel semiconductor memory device including a main control block having an address signal terminal, a clock signal terminal, a command signal terminal and a power
supply terminal as external terminals. An address signal generating section is provided for receiving an external address signal fed to the address signal terminal to generate an internal address signals. A command signal generating section receives an
external command signal fed to the command signal terminal to generate an internal command signal. A clock signal generating section receives an external clock signal fed to the clock signal terminal to generate an internal clock signal. An internal
power supply generating section receives an external supply potential fed to the power supply terminal to generate an internal supply potential. At least one or more than one memory blocks are provided, each having a data input/output terminal and a
power supply terminal for data input/output and including a plurality of memory cells for storing data. A data input/output section sends data to and receives data from the data input/output terminal in response to the internal command signal and in
synchronism with the internal clock signal. The data input/output section is driven by the source power for data input/output fed to the power supply terminal for data input/output. A memory control section writes data in a specific one of the
plurality of memory cells and reads data from a specific one of the plurality of memory cells in response to the internal address signal and in synchronism with the internal clock signal, the memory control section being driven by the internal power
supply potential.
With such a semiconductor memory device, since the main control block has an address signal terminal, a clock signal terminal, a command signal terminal and a power supply terminal as external terminals and each of memory blocks has a data
input/output terminal and a power supply terminal for data input/output, pads can be arranged on the entire chip in a distributed manner. Thus, pads may be arranged along the edges of the chip or the total area for arranging pads may be increased if
compared with a background chip of the same size with pads arranged along a center line. Therefore, the chip can accommodate a greater number of pads and is hence adapted to enhanced functional features and a large memory capacity.
In a further novel semiconductor memory device of the present invention, the address signal generating section includes a row address buffer and column address buffer for producing internal addresses. The command signal generating section may
include a bank switching control circuit for independently writing data in and reading data from each bank, a word line control circuit for controlling word lines, a sense amplifier control circuit for controlling sense amplifiers and a read/write
discriminating circuit for discriminating between a read out mode and a write in mode. The clock signal generating section may include an internal clock generating circuit for generating an internal clock. The internal power supply generating section
may include a DC power supply generating circuit for generating a plurality of internal power supply potentials and the at least one or each of the more than one memory blocks may include a row decoder and a column decoder for selecting a specific memory
cell according to the internal address signal, a sense amplifier for amplifying the data of the memory cell, a bit line control circuit for controlling the sense amplifier and bit line precharge, a data line circuit for transferring data between the
sense amplifier and the data input/output section, a data line circuit control circuit for controlling the data line, an output buffer and an input buffer contained in the data input/output section and a data input/output control circuit for controlling
the data output buffer and the data input buffer.
With such a further novel semiconductor memory device, since not only the memory cells but also the data input/output section of each of the memory blocks have an output buffer and an input buffer, the data lines connecting the memory cells and
the output buffers and the input buffers are distributed among the memory blocks. Since the data lines are closed in each memory block, they can be made short relative to the chip size if compared with the background arrangement of extending each data
line from a memory cell to a region provided for peripheral circuits and disposed among cell arrays. Since the data lines are made short relative to the chip size, the distance separating the input/output buffer and a memory cell of each memory block is
reduced. Thus, an operation of continuously producing data under a condition where a command signal and an address signal are taken in as typically observed in a burst mode can be carried out at high speed. Therefore, there can be provided a novel
semiconductor memory device having a data line arrangement capable of showing a currently available highest level or a dramatically higher level of performance and adapted to enhanced functional features and a large memory capacity.
In a further novel semiconductor memory device of the present invention the internal clock signal, the internal address signal, the internal command signal and the internal power supply potential are fed from the main control block to the at
least one memory block or each of the more than one memory blocks by using a wire in an upper layer located above the wire used for the at least one or each of the than one memory blocks.
With such a further novel semiconductor memory device, the layer for forming the wires connecting the main control block and each of the memory blocks is arranged above and separated from the layer for forming the wires to be used in each memory
block. Thus, the layout of the memory blocks and that of the main control block can be modified independently relative to each other. This by turn can reduce the time period required for developing a semiconductor memory device for greater memory
capacity.
In a further novel semiconductor memory device of the present invention the wire used for the at least one memory block or each of the more than one memory blocks is formed by using a first, second or third metal layer and the wire layer for
connecting the main control block and the at least one memory block or each of the more than one memory blocks is formed by using a fourth metal layer.
With such a further novel semiconductor memory device, since only the fourth metal layer is used for the wire layer for connecting the main control block and the at least one memory block or each of the more than one memory blocks, the wiring
pattern for connecting the main control block and the at least one memory block or each of the more than one memory blocks can be greatly simplified. This in turn can further reduce the time period required for developing a semiconductor memory device
for greater memory capacity.
In a further novel semiconductor memory device of the present invention the at least one memory block or each of the more than one memory blocks is divided into a plurality of banks where data can be written in and read out from independently.
With such a further novel semiconductor memory device, since the at least one memory block or each of the more than one memory blocks is divided into a plurality of banks where data can be written in and read out from independently, the data
precharge period can be apparently wiped out so that the device can be operated from an external element to continuously produce data. This in turn can increase the rate of producing data per unit time.
According to the invention, the above object is also achieved by further providing a novel semiconductor memory device including a semiconductor chip divided into 9 or 3 by 3 regions having an equal area. A main control block is arranged at
least in the central region of the 9 regions and memory blocks controlled by the main control block are arranged respectively in the 8 peripheral regions of the 9 regions, each of the memory blocks including a memory cell array, a data input/output
circuit and a memory control circuit.
With such a further novel semiconductor memory device, since a main control block is arranged at least in the central region and memory blocks are arranged respectively in the 8 peripheral regions, the distance between the main control block and
each of the memory blocks can be minimized. Therefore, signals can get to each of the memory blocks from the main control block in a reduced period of time so that the operating speed of the device can be prevented from becoming slower if a large chip
is used to adapt itself to a large memory capacity.
A semiconductor memory device of the present invention may further feature a connection terminal leading to an external element sealed in a two-dimensionally arranged package therein.
With such a further novel semiconductor memory device, since a connection terminal leading to the external element is arranged two-dimensionally, the device can adapt itself to an increased number of pads.
According to the invention, the above object is also achieved by further providing a novel semiconductor memory device including a semiconductor chip divided into a plurality of memory blocks and input/output terminals and power supply terminals
for data input/output operations arranged respectively in the plurality of memory blocks, the data to be read out from or to be written in one of the plurality of memory blocks moving through the input/output terminal arranged in the same memory block.
With such a further novel semiconductor memory device, since the data to be read out from or to be written in one of the plurality of memory blocks moves through the input/output terminal arranged in the same memory block, the distance for
transferring data can be reduced if compared with a background case where data are transferred from a memory block to some other region.
A semiconductor memory device of the present invention may further feature that a semiconductor chip is divided into 9 or 3 by 3 regions having an equal area. A main control block is arranged at least in the central region of the 9 regions and
memory blocks controlled by the main control block are arranged respectively in the 8 peripheral regions of the 9 regions, each of the plurality memory blocks including a memory a memory cell array, a data input/output circuit and a memory control
circuit.
With such a further novel a semiconductor memory device, since a main control block is arranged at least in the central region and memory blocks are arranged respectively in the 8 peripheral regions, the distance between the main control block
and each of the memory blocks can be minimized.
According to the invention, the above object is further achieved by providing a method of laying out a semiconductor memory device including steps of preparing a circuit pattern for a memory block including a memory cell array, a data
input/output circuit and a memory control circuit and a circuit pattern for a main control block for controlling the memory block, arranging 9 or 3 by 3 regions, each having a size same as that of the circuit pattern of a memory block or that of the
circuit pattern of a main control block, whichever is larger, and arranging eight such circuit patterns for memory blocks respectively in the 8 peripheral regions and a circuit pattern for a main control block at least in the central region.
With such a novel method of laying out a semiconductor memory device, since there are arranged 9 or 3 by 3 regions, each having a same size as that of the circuit pattern of a memory block or that of the circuit pattern of a main control block,
whichever is larger, the laying out operation can be conducted with limited restrictions in terms of space. For instance, if a large circuit pattern is used for the memory blocks, a free space can be provided for the circuit pattern of the main control
block so that the design of the latter may be modified without being subjected to significant restrictions typically in terms of a size of the transistors and that of booster capacitors. Additionally, the free space provided for the main control block
may be used partly for arranging a test mode circuit such as a built-in self test circuit. Still additionally, the free space provided for the main control block may be used for additional circuits that may be added in the future. Incorporating an
additional functional feature typically requires a free space in the device and the space of the main control block may be used for such an additional functional feature. Thus, such a novel method of laying out a semiconductor memory device is
particularly effective for incorporating an additional function feature into a semiconductor memory device without modifying the arrangement of memory blocks in the semiconductor memory device.
If, to the contrary, a large circuit pattern is used for the main control block, a free space is provided for the circuit pattern of the memory blocks. The free space may be used for modifying a design of the memory blocks particularly in terms
of the size of the memory cells, that of the sense amplifiers and/or that of the decoders.
According to the invention, the above object is further achieved by providing a semiconductor memory device including a main control block for receiving an external address signal, an external command signal, an external clock signal and an
external power supply potential and sending out an internal address signal, an internal command signal, an internal clock signal and an internal power supply potential. A plurality of memory blocks are controlled by the main control block, each of the
plurality of memory blocks receiving the internal address signal, the internal command signal, the internal clock signal and the internal power supply potential, writing an input data supplied from an external element in a memory cell selected for data
writing in synchronism with the internal clock signal and sending out to an external element an output data from a memory cell selected for data reading in synchronism with the internal clock signal. An external pad group is arranged in the main control
block for receiving the external address signal, the external command signal, the external clock signal and the external power supply potential and an external pad group is arranged in each of the plurality of memory blocks for receiving the input data
and the output data.
With such a novel semiconductor memory device, an external pad group is arranged in a main control block for receiving an external address signal, an external command signal, an external clock signal and an external power supply potential and an
external pad group is arranged in each of a plurality of memory blocks for receiving an input data and an output data. With such an arrangement, the area for arranging pads on the chip can be increased if compared with a background device where a pad
group for receiving an external address signal, an external command signal, the external clock signal and an external power supply potential as well as an input data and an output data is collectively arranged between memory cell arrays or in a
peripheral circuit block arranged along an edge of the chip. This means that a larger number of pads can be arranged on a chip.
According to the invention, the above object is further achieved by providing a novel semiconductor memory device including a main control block for receiving an external address signal, an external command signal, an external clock signal and an
external power supply potential and sending out an internal address signal, an internal command signal, an internal clock signal and an internal power supply potential. A plurality of memory blocks are controlled by the main control block, each of the
plurality of memory blocks receiving the internal address signal, the internal command signal, the internal clock signal and the internal power supply potential, writing an input data supplied from an external element in a memory cell selected for data
writing in synchronism with the internal clock signal and sending out to an external element an output data from a memory cell selected for data reading in synchronism with the internal clock signal. A wire group is formed by using an upper wire layer
located above the wire group formed in the inside of each of the plurality of memory blocks and connecting the main control block and each of the plurality of memory blocks to feed signals for controlling the plurality of memory blocks.
With such a novel semiconductor memory device, a wire group is formed by using an upper wire layer located above the wire group formed in the inside of each of the plurality of memory blocks and connecting the main control block and each of the
plurality of memory blocks to feed signals for controlling the plurality of memory blocks. Thus, the memory blocks and the main control block can be designed independently relative to each other so that the efficiency of developing a new semiconductor
memory device of the type under consideration can improved if compared with a background case where memory blocks and a control circuit are designed in a consolidated manner. Thus, the time required for developing such a device can be reduced. The main
control block is principally formed of logic circuits to form a logic IC. On the other hand, each of the memory blocks is principally formed of memory circuits to form a memory IC. Therefore, with such a novel semiconductor memory device for which the
memory blocks and the main control block can be designed independently relative to each other, the operation of designing the device can be assigned to engineers who specialize in designing particular respective blocks so that the device may be provided
with enhanced functional features and designed within a reduced period of time. For instance, since the main control block is a logic IC, a large capacity semiconductor memory device that can be mounted on a processor can be derivatively designed on the
basis of a semiconductor memory device according to the invention.
According to the invention, the above object is further achieved by providing a novel semiconductor memory device including a main control block for receiving an external address signal, an external command signal, an external clock signal and an
external power supply potential and sending out an internal address signal, an internal command signal, an internal clock signal and an internal power supply potential. A plurality of memory blocks are controlled by the main control block, each of the
plurality of memory blocks receiving the internal address signal, the internal command signal, the internal clock signal and the internal power supply potential, writing an input data supplied from an external element in a memory cell selected for data
writing in synchronism with the internal clock signal and sending out to an external element an output data from a memory cell selected for data reading in synchronism with the internal clock signal. Supply wires connect the main control block and each
of the plurality of memory blocks for feeding each of the plurality of memory blocks with the internal address signal, the internal command signal, the internal clock signal and the internal power supply potential generated by the main control block and
data transfer circuits are arranged respectively in the plurality of memory blocks, each connecting the external pad for receiving the input data and the output data and the memory cell.
With such a novel semiconductor memory device, data transfer circuits for electrically connecting external pads for receiving input and output data and respective memory cells are distributed among a plurality of memory blocks. Since the data
transfer circuits are closed in the respective memory blocks, the length of the data transfer circuits per unit chip size can be reduced if compared with a background case where they are extended to the space separating memory cell arrays or the
peripheral circuit block arranged along an edge of the chip so that the data transfer operation can be carried out at high speed.
According to the invention, the above object is a further achieved by providing a novel semiconductor memory device including a semiconductor chip divided into 9 or 3 by 3 region having an equal area. A main control block is arranged at least in
the central region of the 9 regions for receiving an external address signal, an external command signal, an external clock signal and an external power supply potential and sending out an internal address signal, an internal command signal, an internal
clock signal and an internal power supply potential. Memory blocks are arranged respectively in the 8 peripheral regions of the 9 regions and are controlled by the main control block, each of the plurality of memory blocks receiving the internal address
signal, the internal command signal, the internal clock signal and the internal power supply potential, writing an input data supplied from an external element in a memory cell selected for data writing in synchronism with the internal clock signal and
sending out to an external element an output data from a memory cell selected for data reading in synchronism with the internal clock signal.
With such a novel semiconductor memory device, a semiconductor chip is divided into 9 or 3 by 3 regions having an equal area and a main control block is arranged at least in the central region of the 9 regions while memory blocks are arranged
respectively in the 8 peripheral regions. With this arrangement, the memory blocks are separated from the main control block with a substantially same distance to minimize the differences in the delay time of the controls signals and the internal power
supply potential generated by the main control block and fed to the memory blocks. Thus, the main control block can control each of the memory blocks very quickly.
According to the invention, the above object is further achieved by providing a novel semiconductor memory device including a semiconductor chip divided into 9 or 3 by 3 regions having an equal area, a main control block arranged at least in the
central region of the 9 regions for receiving an external address signal, an external command signal, an external clock signal and an external power supply potential and sending out an internal address signal, an internal command signal, an internal
clock signal and an internal power supply potential. Memory blocks are arranged respectively in the 8 peripheral regions of the 9 regions and are controlled by the main control block, each of the plurality of memory blocks receiving the internal address
signal, the internal command signal, the internal clock signal and the internal power supply potential, writing an input data supplied from an external element in a memory cell selected for data writing in synchronism with the internal clock signal and
sending out to an external element an output data from a memory cell selected for data reading in synchronism with the internal clock signal. An external pad group is arranged in the main control block for receiving the external address signal, the
external command signal, the external clock signal and the external power supply potential. An external pad group is arranged in each of the plurality of memory blocks for receiving the input data and the output data. Supply wires connect the main
control block and each of the plurality of memory blocks for feeding each of the plurality of memory blocks with the internal address signal, the internal command signal, the internal clock signal and the internal power supply potential generated by the
main control block and data transfer circuits arranged respectively in the plurality of memory blocks, each connecting the external pad for receiving the input data and the output data and the memory cell.
With such a novel semiconductor memory device, a semiconductor chip is divided into 9 or 3 by 3 regions having an equal area and a main control block is arranged at least in the central region of the 9 regions while memory blocks are arranged
respectively in the 8 peripheral regions. With this arrangement, the memory blocks are separated from the main control block with a substantially same distance to minimize the differences in the delay time of the controls signals and the internal power
supply potential generated by the main control block and fed to the memory blocks. Thus, the main control block can control each of the memory blocks very quickly.
Additionally, an external pad group is arranged in a main control block for receiving an external address signal, an external command signal, an external clock signal and an external power supply potential and an external pad group is arranged in
each of a plurality of memory blocks for receiving an input data and an output data. With such an arrangement, the area for arranging pads on the chip can be increased if compared with a background device where a pad group for receiving an external
address signal, an external command signal, an external clock signal and an external power supply potential as well as an input data and an output data is collectively arranged between memory cell arrays or in a peripheral circuit block arranged along an
edge of the chip. This means that a larger space can be provided for chip pads.
Still additionally, data transfer circuits for electrically connecting external pads for receiving input and output data and respective memory cells are distributed among a plurality of memory blocks. Since the data transfer circuits are closed
in the respective memory blocks, the length of the data transfer circuits per unit chip size can be reduced if compared with a background case where they are extended to the space separating memory cell arrays or the peripheral circuit block arranged
along an edge of the chip so that the data transfer operation can be carried out at high speed.
Finally, the data transfer circuits are formed by using only a wire layer located under the wire layer connecting the main control block and each of the plurality of memory blocks and forming feed wires for feeding signals for controlling the
plurality of memory blocks. Thus, the main control block and the memory blocks can be designed independently relative to each other to improve the efficiency of developing a new semiconductor memory device of the type under consideration if compared
with a background case where memory blocks and a main control block are designed in a consolidated manner.
According to the invention, the above object is further achieved by providing a novel semiconductor memory device including a semiconductor chip divided into 9 or 3 by 3 regions having an equal area. A logic integrated circuit arranged in the
central region of the 9 regions and memory integrated circuits are arranged respectively in the 8 peripheral regions of the 9 regions except the central region.
With such a novel semiconductor memory device, a semiconductor chip is divided into 9 or 3 by 3 regions having an equal area and a logic integrated circuit is arranged at least in the central region of the 9 regions while memory integrated
circuits, each including a memory cell array, are arranged respectively in the 8 peripheral regions except the central region. With this arrangement, the memory integrated circuits are separated from the logic integrated circuit with a substantially
same distance to minimize the differences in the distance. Thus, a single logic integrated circuit can simultaneously control the 8 memory integrated circuits to minimize the delay time of the controls signals getting to the 8 memory integrated
circuits. Therefore, it provides an arrangement of 8 memory integrated circuits in a semiconductor memory device that can make the device operate at the highest possible speed.
According to the invention, the above object is further achieved by providing a novel semiconductor memory device includ | | |
