 |
Description  |
|
|
BACKGROUND OF THE INVENTION
The present invention relates to a technology for simultaneously testing a
plurality of integrated circuits formed on a semiconductor wafer in a
wafer condition.
Advances in size reduction and cost reduction of recent electronic
components incorporating semiconductor IC (integrated circuit) devices are
so remarkable that requirements to the size reduction and cost reduction
of the semiconductor IC devices are becoming more severe.
In general, a manufacturing of a semiconductor IC device is as follows.
First of all, a semiconductor chip and a lead frame are electrically
connected with each other by means of a bonding wire. Thereafter, the
semiconductor chip is sealed by resin or ceramic and then mounted on a
printed board. However, the requirements of reducing the size of an
electronic component have introduced a method of directly mounting on a
circuit board a semiconductor IC device in a bare chip or chip condition
to guarantee quality at low cost. The bare chip or chip condition
generally represents a condition of semiconductor IC device which is just
cut off a semiconductor wafer.
In order to guarantee quality of bare chips, it is necessary to execute a
burn-in screening of a semiconductor IC device in the wafer condition.
However, the burn-in screening of the semiconductor wafer is complicated in
handling the semiconductor wafer; thus, the requirement to low cost could
not be satisfied. Furthermore, executing the burn-in screening of the
plural bare chips on a semiconductor wafer is time-consuming since it
requires to execute the burn-in screening separately and repeatedly one by
ene or group by group. Thus, in view of time and cost, it does not bring
practical merits.
Accordingly, it is earnestly required to realize a simultaneous execution
of the burn-in screening of all the bare chips in the wafer condition.
FIG. 32 is a schematic view showing a testing method of a semiconductor
wafer using a conventional prober. As shown in FIG. 32, a semiconductor
wafer 202 is fixed on a wafer stage 201 provided in the prober. A probe
card 204, having probe needles 203, - - - , 203 made of for example
tungsten, is disposed above the semiconductor wafer 202. These probe
needles 203, - - - , 203 are brought into contact with IC terminals on the
semiconductor wafer 202, so that an electric power voltage or signal can
be supplied to the integrated circuit by means of a tester or the like to
detect an output signal from the integrated circuit chip by chip. For
testing the same kind of integrated circuits in a short time, a full
automatic prober is normally used since it has an alignment function and
is capable of automatically executing a measurement of chip one by one. In
FIG. 32, a reference numeral 205 represents a wiring pattern and a
reference numeral 206 represents an external electrode terminal.
Hereinafter, a conventional testing method of a semiconductor wafer using a
full automatic prober will be explained with reference to FIGS. 32 and 33.
First of all, in a step SB1, the semiconductor wafer 202 is automatically
transported from a wafer carrier onto the wafer stage 201. Next, in a step
SB2, positioning of the semiconductor wafer 202 is carried out using a CCD
camera or the like so that IC terminals on the semiconductor wafer 202 can
be brought into contact with the probe needles 203, - - - 203. Then, in a
step SB3, the wafer stage 201 is shifted below the probe card 204 so that
the semiconductor wafer 202 is placed below the probe card 204.
Subsequently, in a step SB4, the probe needles 203, - - - , 203 are brought
into contact with the IC terminals on the semiconductor wafer 202. An
electric power voltage or signal is applied to the integrated circuit to
measure an output signal from the integrated circuit, thereby executing a
test of the integrated circuit. After finishing the test of one integrated
circuit, the wafer stage 201 is shifted to the next integrated circuit.
Then, the probe needles 203, - - - , 203 are brought into contact with the
terminals of the next integrated circuit to execute a measurement of the
next integrated circuit.
According to the conventional testing method of a semiconductor wafer using
a full automatic prober, a plurality of integrated circuits on the
semiconductor wafer 202 are successively measured in the manner
above-described. When the test of all the integrated circuits is
completed, the semiconductor wafer 202 is returned from the wafer stage
201 to the wafer carrier in a step SB5. For a plurality of semiconductor
wafers 202, - - - , 202, above-described steps are repeatedly executed to
accomplish a measurement of each semiconductor wafer 202. When the
measurement of all the semiconductor wafers 202 is finished, operation of
the full automatic prober ends.
A method of shortening a test time per chip would be, for example, to
provide a self test circuit (i.e. BIST circuit) to execute the burn-in
screening (high-speed operation) of memories such as DRAM by means of a
prober.
Executing the burn-in screening processing in the wafer condition according
to the previously-described testing method of a semiconductor wafer using
a prober would require a time not longer than 1 minute in total for the
shifting of the semiconductor wafer 202 in the procedures of the steps
SB1, SB3 and SB5 and the positioning of the semiconductor wafer 202 in the
step SB2. However, the burn-in screening in the step SB4 usually requires
several to several tens hours. The conventional testing method of a
semiconductor wafer using a prober is disadvantageous in that it
necessitates to test semiconductor wafers one by one. Accordingly, it
takes an extremely long time to test a great amount of semiconductor
wafers. This will results in a huge increase of cost for manufacturing an
LSI chip.
Another disadvantage of the testing operation using an automatic prober is
an exclusive usage of the probe during tests, because the alignment
function cannot be used for tests for other kinds of semiconductor wafers
or other purposes.
Providing a BIST circuit for shortening a test time per chip, applied to
DRAM or the like, leads to an increase of a chip area and reduces the
number of chips per wafer, thus causing a problem of increasing chip cost.
To execute the burn-in screening of bare chips at a time in the wafer
condition, it is necessary to simultaneously apply an electric power
voltage or signal to a plurality of chips formed on the same wafer, to
operate all of these plural chips. To this end, it will be necessary to
prepare a probe card having numerous probe needles (e.g. several thousands
or more). However, the conventional needle type probe card cannot meet
such a need in view of great number of pins and cost increase.
Proposed to solve such a problem is a thin film type probe card having
bumps on a flexible substrate (Refer to Nitto Technical Reports Vol.28,
No.2 (October 1990) PP. 57-62)
Hereinafter, the burn-in screening using a flexible substrate with bumps
will be explained.
FIGS. 34(a) and 34(b) are cross-sectional views illustrating the probing
condition when a flexible substrate with bumps is used. In FIGS. 34(a) and
34(b), a reference numeral 211 represents a probe card which comprises a
polyimide substrate 218, a wiring layer 217 formed on the polyimide
substrate 218, bump electrodes 216, - - - , 216, and a through hole wiring
connecting the wiring layer 217 and the bump electrodes 216, - - - , 216.
As illustrated in FIG. 34(a), the probe card 211 is pushed against a
semiconductor wafer 212 serving as a tested substrate so that a pad 215 on
the semiconductor wafer 212 is electrically connected to a corresponding
bump 216 of the probe card 211. If testing condition is in a room
temperature, a test will be feasible in this condition by simply applying
an electric power voltage or signal to the bump 216 via the wiring layer
217.
However, a diameter of the semiconductor wafer 212 possibly increases up
to, foe example, 6 inches in the probing using the conventional probe card
211, causing deflection of the semiconductor wafer 212 and/or unevenness
in height of the bump 216 which lead to a first problem of making some of
electrical connections useless between the bumps 216, - - - , 216 and the
pads 215, - - - , 215.
The burn-in screening generally requires a step of increasing the
temperature of the semiconductor wafer 212 to execute temperature
acceleration. FIG. 34(b) shows a cross-sectional structure of the
semiconductor wafer 212 heated from the room temperature 25.degree. C. to
125.degree. C. In FIG. 34(b), the left-hand portion shows condition of a
center of the semiconductor wafer 212, while the right-hand portion shows
condition of a periphery of the semiconductor wafer 212.
Polyimide constituting the polyimide substrate 218 has a thermal expansion
coefficient larger than that of silicon constituting the semiconductor
wafer 212. (More specifically, the thermal expansion coefficient of
polyimide is 16.times.10.sup.-6 /.degree. C., while the thermal expansion
coefficient of silicon is 3.5.times.10.sup.-6 /.degree. C.) Thus,
dislocation between the bump 216 and its corresponding pad 215 is found at
the peripheral portion of the semiconductor wafer 212. More specifically,
if the semiconductor wafer 212 of 6 inches and the probe card 211 are
aligned in position at a room temperature and then heated to 100.degree.
C., the probe card 211 will cause a thermal expansion of 160 .mu.m while
the semiconductor wafer 212 will cause a thermal expansion of 35 .mu.m. In
other words, a dislocation between the pad 215 and the bump 216 will
increase up to an approximately 125 .mu.m at the outermost periphery of
the semiconductor wafer 212. Such a dislocation due to difference of
thermal expansion is so serious that electrical connection between the pad
215 and its corresponding bump 216 cannot be maintained in the peripheral
region of the semiconductor wafer 212.
As explained above, according to the conventional burn-in screening, the
semiconductor wafer is heated during the burn-in screening. The probe card
brought into contact with the semiconductor wafer is also heated. Thus,
difference of thermal expansion coefficients between the semiconductor
wafer and the probe card causes a serious dislocation therebetween,
resulting in a second problem that electrical connection between a pad and
its corresponding bump cannot be maintained at the periphery of the
semiconductor wafer.
To execute the burn-in screening of bare chips in the wafer condition, it
is necessary to operate each bare chip by simultaneously applying an
electric power voltage or signal to a plurality of bare chips formed on a
single semiconductor wafer. However, supplying an electric power voltage
or signal to each bare chip independently is not practical in view of cost
since the number of wiring patterns exclusively formed on the
semiconductor wafer increases up to several thousands or several tens
thousands. To reduce the number of independently or exclusively provided
wiring patterns, it is necessary to commonly use the wiring patterns as
many as possible.
However, if extraordinary current flows through one bare chip connected to
such a common wiring pattern, adverse effect of extraordinary current will
spread to other bare chips associated. Thus, it becomes impossible to
execute an ordinary burn-in screening.
Accordingly, in executing the burn-in screening, it is necessary to
electrically remove such an extraordinary bare chip from the common wiring
pattern.
Hereinafter, a method disclosed in the Unexamined Japanese Patent
Application No. HEI 1-227467/1989 will be explained as one example of the
burn-in screening of bare chips in the wafer condition.
FIG. 35 shows one of plural bare chips formed on a semiconductor wafer. In
FIG. 35, a reference numeral 240 represents a bare chip, a reference
numeral 243 represents an electric power source pad of the bare chip 240,
a reference numeral 244 represents a GND pad of the bare chip 240, a
reference numeral 241 represents a burn-in electric power source pad, and
a reference numeral 242 represents a P-channel type transistor. The
transistor 242 has a drain connected to the burn-in electric power source
pad 241 and a source connected to the electric power source pad 243.
Furthermore, in FIG. 35, a reference numeral 245a represents a first pad
connected to the gate of transistor 242, and reference numerals 245b and
245c represent second and third pads respectively connected to the first
pad 245a via a thin aluminum pattern of, for example, 3 .mu.m width. A
first resistance 246a is interposed between the GND pad 244 and the second
pad 245b. This first resistance 246a has a relatively low resistant value
(e.g. 10 k.OMEGA.). A second resistance 246b is interposed between the
burn-in electric power source pad 241 and the third pad 245c. This second
resistance 246b has a relatively high resistant value (e.g. 100 k.OMEGA.).
First of all,-before a burn-in screening, a wafer test is executed by
probing electric power source pad 243, GOND pad 244, first to third pads
245a-245c using a stationary probe needle (not shown) connected to an
external measurement device (not shown) . The external measurement device
applies an electric power voltage to the electric power source pad 243 and
applies a GND voltage to the GND pad 244. Furthermore, the first pad 245a
is given an "H" level signal. As the transistor 242 is in an OFF condition
under such a condition, no current flows between the electric power source
pad 243 and the burn-in pad 241. Thus, a test of the bare chip 240 is
feasible.
When the bare chip 240 is found to be a non-defective as a result of the
test of the bare chip 240, the next bare chip is subsequently tested. On
the contrary, if the bare chip 240 is found to be a defective, the
external measurement device supplies large current (e.g. 100 mA) between
the first pad 245a and the second pad 245b to fuse the shin aluminum
pattern interposed between the first pad 245a and the second pad 245b
before going on a test of the next bare chip.
By doing the wafer test in this manner before the burn-in screening, the
burn-in screening can be effectively carried out. More specifically, when
the burn-in electric power source pad 241 is applied an electric voltage
in the burn-in screening, the transistor 242 is turned on in the case the
bare chip 240 is found a non-defective in the wafer test because the gate
voltage of the transistor 242 becomes an "L" level due to existence of the
second resistance 246b having a resistant value larger than that of the
first resistance 246a. Thus, the burn-in voltage is supplied to the
electric power source pad 243 through the transistor 242. On the other
hand, the thin aluminum pattern between the first pad 245a and the second
pad 245b is fused off in a case the bare chip 240 is found a defective in
the wafer test. Therefore, the gate voltage of the transistor 242 becomes
an "H" level, and the transistor 242 is turned off. Thus, the burn-in
voltage is not supplied to the electric power source pad 243, preventing
electric current from flowing through the defective bare chip 240.
As described above, electric power source current is surely prevented from
flowing through the defective chip even if an electric voltage is applied
to the burn-in electric power source pad 241. Hence, adverse effect is not
given to the non-defective chips in the burn-in screening.
However, above-described arrangement requires to form on each bare chip 240
excessive elements such as transistor 242, first and second resistances
246a, 246b, burn-in electric power source pad 241, first to third pads
245a-245c and aluminum pattern acting as a fuse. Furthermore, an electric
voltage is applied through the transistor 242 in the burn-in screening
and, therefore, an electric voltage applied to the burn-in electric power
source pad 241 is not directly applied to the internal electric power
source. Thus, a third problem arises in that a significant voltage drop is
induced in the bare chip 240.
SUMMARY OF THE INVENTION
Accordingly, in view of above-described problems encountered in the prior
art, a first object of the present invention is to surely bring all the
probe terminals of a probe sheet into contact with all the testing
terminals of a semiconductor wafer even if a diameter of the semiconductor
wafer is increased, and to simultaneously execute a burn-in screening with
respect to a plurality of semiconductor wafer.
A second object of the present invention is to surely bring the bump of the
probe sheet into contact with the testing terminal of the semiconductor
wafer even in the periphery of a large-diameter semiconductor wafer in the
burn-in screening.
A third object of the present invention is to surely prevent a defective
chip from being supplied with electric power voltage in the burn-in
screening.
A technology for accomplishing the first object will be hereinafter
described.
The present invention provides a first semiconductor wafer package
comprising: a retainer board for holding a semiconductor wafer having a
plurality of integrated circuit terminals for testing a semiconductor
chip; a probe sheet confronting with the retainer board and having a
plurality of probe terminals to be electrically connected to the
integrated circuit terminals corresponding thereto; an insulating
substrate provided on the probe sheet in opposed relation to the retainer
board and having a wiring electrically connected to the plural probe
terminals; an external electrode electrically connected to the wiring for
receiving an electric power voltage or signal for test; an elastic member
interposed between the probe sheet and the insulating substrate; and
pressing means for pressing at least either of the retainer board and the
insulating substrate in such a manner that the retainer board and the
probe sheet are brought into so closer relationship that each integrated
circuit terminal of the semiconductor wafer held by the retainer board is
electrically connected to the probe terminals of the probe sheet which
correspond thereto.
According to the first semiconductor wafer package, when the pressing means
presses at least either of the retainer board and the insulating
substrate, the retainer board and the probe sheet are brought into so
closer relationship that each integrated circuit terminal of the
semiconductor wafer held by the retainer board is electrically connected
to its corresponding probe terminal of the probe sheet. In this case, the
probe sheet is pressed via the elastic member; therefore, the elastic
member absorbs unevenness of probe terminal height of probe sheet. With
this arrangement, each integrated circuit terminal of the semiconductor
wafer is surely connected to each probe terminal of the probe sheet, and a
pressing force is uniformly applied on each probe terminal. Thus, a
contact resistance between the integrated circuit terminal and the probe
terminal can be reduced, and a uniform input waveform can be supplied to
each integrated circuit terminal of the semiconductor wafer, thus
improving detecting accuracy.
The elastic member, interposed between the probe sheet and the insulating
substrate, acts as cushioning member preventing the semiconductor wafer
from being damaged when the insulating substrate is disposed on the
semiconductor wafer or when the semiconductor wafer package is
transported.
By controlling the temperature of the semiconductor wafer package, the
temperature of the semiconductor wafer can be controlled. When an electric
power voltage or signal is input to the external electrode for testing,
the testing electric power voltage or signal is supplied to the probe
terminal via the wiring of the insulating substrate, and subsequently
supplied to the integrated circuit terminal of the semiconductor wafer.
Accordingly, it becomes possible to separate an alignment step of aligning
the semiconductor wafer and the probe sheet, an temperature control step
of controlling the temperature of the semiconductor wafer, and an input
step of inputting the electric power voltage or signal to the integrated
circuit of the semiconductor wafer from each other. Thus, numerous
semiconductor wafers can be tested at the same time.
It is preferable that the first semiconductor wafer package further
comprises a seal member disposed between the retainer board and the
insulating substrate for forming a hermetical space defined between the
retainer board and the insulating substrate. And, the pressing means is
high-pressure fluid of gas or liquid supplied to the hermetical space.
With this arrangement, when the high-pressure fluid of gas or liquid is
supplied to the hermetical space, the insulating substrate presses the
probe sheet toward the semiconductor wafer and, therefore, each integrated
circuit terminal of the semiconductor wafer can be surely connected to its
corresponding probe terminal.
It is further preferable that in the first semiconductor wafer package that
the retainer board has means for sucking the semiconductor wafer and
fixing the semiconductor wafer to the retainer board.
With this arrangement, the semiconductor wafer can be surely fixed to the
retainer board.
The present invention provides a second semiconductor wafer package
comprising: a retainer board for holding a semiconductor wafer having a
plurality of integrated circuit terminals for testing a semiconductor
chip; a probe sheet confronting with the retainer board and having a
plurality of probe terminals to be electrically connected to the
integrated circuit terminals corresponding thereto; an insulating
substrate provided on the probe sheet in opposed relation to the retainer
board and having a wiring electrically connected to the plural probe
terminals; an external electrode electrically connected to the wiring for
receiving an electric power voltage or signal for test; and temperature
detecting means for detecting temperature of the semiconductor wafer held
by the retainer board.
According to the second semiconductor wafer package, in the same manner as
in the first semiconductor wafer package, not only numerous semiconductor
wafers can be simultaneously tested but the temperature of each
semiconductor wafer can be detected by the temperature detecting means
when the numerous semiconductor wafers are simultaneously tested, thereby
assuring temperature control of the semiconductor wafer.
The present invention provides a third semiconductor wafer package
comprising: a retainer board for holding a semiconductor wafer having a
plurality of integrated circuit terminals for testing a semiconductor
chip; a probe sheet confronting with the retainer board and having a
plurality of probe terminals electrically connected to their corresponding
integrated circuit terminals; an insulating substrate provided on the
probe sheet in opposed relation to the retainer board and having a first
wiring electrically connected to the plural probe terminals; a pressing
board provided on the probe sheet in opposed relation to the retainer
board and having a second wiring electrically connected to the first
wiring; a seal member disposed between the retainer board and the pressing
board for forming a hermetical space defined between the retainer board
and the pressing board; pressure reducing means for reducing pressure of
the hermetical space in such a manner that the retainer board and the
probe sheet are brought into so closer relationship that each integrated
circuit terminal of the semiconductor wafer held by the retainer board is
electrically connected to the probe terminal of the probe sheet which
corresponds thereto; and an external electrode electrically connected to
the second wiring for receiving an electric power voltage or signal for
test.
According to the third semiconductor wafer package, numerous semiconductor
wafers can be simultaneously tested in the same manner as in the first
semiconductor wafer package. Furthermore, when the pressure of the
hermetical space formed between the retainer board and the pressing board
is reduced, the retainer board and the probe sheet are brought into so
closer relationship that each integrated circuit terminal of the
semiconductor wafer is electrically connected to its corresponding probe
terminal of the probe sheet.
The present invention provides a fourth semiconductor wafer package
comprising: a retainer board for holding a semiconductor wafer having a
plurality of integrated circuit terminals for testing a semiconductor
chip; a probe sheet confronting with the retainer board and having a
plurality of probe terminals to be electrically connected to the
integrated circuit terminals corresponding thereto; an insulating
substrate provided on the probe sheet in opposed relation to the retainer
board and having a wiring electrically connected to the plural probe
terminals; a rigid board provided on the insulating substrate in opposed
relation to the retainer board; a pressing bag made of elastic member
interposed between the insulating substrate and the rigid member; fixing
means for fixing the insulating substrate and the rigid board in such a
manner that the pressing bag is interposed between the insulating
substrate and the rigid board; a casing accommodating the retainer board,
the probe sheet, the insulating substrate, the rigid board, the pressing
bag and the fixing means; pressure reducing means for reducing pressure of
gas in the casing in such a manner that the retainer board and the probe
sheet are brought into so closer relationship that each integrated circuit
terminal of the semiconductor wafer held by the retainer board is to be
electrically connected to the probe terminals of the probe sheet which are
corresponding thereto; and an external electrode electrically connected to
the wiring for receiving an electric power voltage or signal for test.
According to the fourth semiconductor wafer package, numerous semiconductor
wafers can be simultaneously tested in the same manner as in the first
semiconductor wafer package.
When the inside pressure of the casing is reduced, the pressing bag
interposed between the insulating substrate and the rigid member inflates.
An inflation of the pressing bag is converted into a pressing force
transmitted to the probe sheet via the insulating substrate. Thus, the
probe sheet and the semiconductor wafer are brought into so closer
relationship that each probe terminal of the probe sheet can be surely
electrically connected to its corresponding integrated circuit terminal of
the semiconductor wafer.
It is preferable that the fourth semiconductor wafer package further
comprises communicating means for communicating the inside of the pressing
bag to the outside of the casing. With this arrangement, even if the
inside pressure of the casing is increased by air introduced into the
casing, it is possible to increase the pressure of the pressing bag so as
to constantly maintain a pressing force applied from the pressing bag to
the probe sheet via the insulating substrate. Hence, an electrical
connection between each probe terminal of the probe sheet and each
integrated circuit terminal of the semiconductor wafer can be electrically
maintained.
It is further preferable that the first to fourth semiconductor wafer
packages comprise temperature control means for controlling the
temperature of the semiconductor wafer held by the retainer board.
The present invention provides an apparatus for connecting a plurality of
testing integrated circuit terminals of a semiconductor wafer and a
plurality of probe terminals, comprising: a casing: a partition board
slidably housed in the casing for separating an inside space of the casing
into first and second regions; a retainer board, provided in the first
region, for holding the semiconductor wafer; an insulating substrate
provided in the first region so as to confront with the retainer board and
having a plurality of probe terminals; and pressure control means for
increasing pressure of the second region compared with pressure of the
first region so that the partition board shifts toward the first region
until each probe terminal of the insulating substrate is electrically
connected to its corresponding testing integrated circuit terminal of the
semiconductor wafer held by the retainer board.
According to this connecting apparatus, when the pressure of the second
region becomes higher than that of the first region, the diaphragm shifts
toward the first region. Thus, each probe terminal of the insulating
substrate is electrically connected to each testing integrated circuit
terminal of the semiconductor wafer held by the retainer board. In other
words, this connecting device requires the semiconductor wafer package to
have no pressing means for bringing the probe sheet into closer
relationship to the semiconductor wafer, for electrically connecting each
probe terminal of the insulating substrate to each testing integrated
circuit terminal of the semiconductor wafer.
The present invention provides a method for connecting a plurality of
testing integrated circuit terminals of a semiconductor wafer and a
plurality of probe terminals of a probe sheet, comprising: a first step of
holding the semiconductor wafer at a central region of a retainer board
having an elastic seal member along a periphery thereof; a second step of
disposing the probe sheet on the semiconductor wafer in such a manner each
probe terminal confront with its corresponding testing integrated circuit
terminal; a third step of disposing a pressing board on the elastic seal
member of the retainer board to form a hermetical space defined by the
retainer board, the elastic seal member and the pressing board; and a
fourth step of reducing pressure of the hermetical space in such a manner
that the retainer board and the pressing board are brought into so closer
relationship that each probe terminal is electrically connected to its
corresponding testing integrated circuit terminal.
According to this connecting method, when the pressure of the hermetical
space is reduced, the retainer board and the pressing board are brought
into so closer relationship that each probe terminal of the probe sheet is
electrically connected to its corresponding testing integrated circuit
terminal of the semiconductor wafer held by the retainer board.
It is preferable that the above-described connecting method further
comprises a pressing step, between the second step and the third step, for
pressing at least either of the retainer board and the pressing board in
advance so that each testing integrated circuit terminal is electrically
connected to its corresponding probe terminal.
With this arrangement, the pressure of the hermetical space can be reduced
in a condition that each testing integrated circuit terminal is brought
into contact with each probe terminal. Thus, no positional dislocation is
caused between the testing integrated circuit terminal and the probe
terminal.
The present invention provides a testing method of a semiconductor
integrated circuit comprising: a first step of holding a semiconductor
wafer by a retainer board, the semiconductor wafer having a plurality of
integrated circuit terminals for testing a semiconductor chip; a second
step of disposing a probe sheet having a plurality of probe terminals on
the semiconductor wafer in such a manner that each probe terminal is
electrically connected to its corresponding integrated circuit terminal; a
third step of disposing an insulating substrate having wiring electrically
connected to each probe terminal and an external electrode receiving an
electric power voltage or signal for test in such a manner that each probe
terminal is electrically connected to its corresponding external electrode
by way of the wiring; and a fourth step of inputting an electric power
voltage or signal to the external electrode to input the electric power
voltage or signal to the integrated circuit terminal by way of the wiring
and the plural probe terminals.
According to the testing method of the semiconductor integrated circuit,
when an electric power voltage or signal is input to the external
electrode, the electric power voltage or signal is input to the integrated
circuit terminal of the semiconductor wafer by way of the wiring of the
insulating substrate and the probe terminal of the probe sheet. Therefore,
it becomes possible to separate the alignment step of aligning the
semiconductor wafer and the probe sheet from the input step of inputting
the electric power voltage or signal to the integrated circuit of the
semiconductor wafer. Hence, numerous semiconductor wafers can be
simultaneously tested.
In the testing method of the semiconductor integrated circuit, it is
preferable that the first step comprises a step of heating the
semiconductor wafer held by the retainer board to a predetermined
temperature, or there is further provided a fifth step of heating the
semiconductor wafer held by the retainer board to a predetermined
temperature.
By doing so, the burn-in screening of the semiconductor wafer can be
executed.
Hereinafter, a probe card accomplishing the above-described second object
and its manufacturing method will be explained.
The present invention provides a first probe card testing electric
characteristics of a chip formed on a semiconductor wafer, comprising: a
flexible substrate made of elastic member having a probe terminal on one
main surface thereof; and a rigid member fixing the periphery of the
flexible substrate, wherein the flexible substrate is fixed by the rigid
member in a condition that always maintains tensile distortion within a
temperature range from the room temperature to a testing temperature.
According to the first probe card, the flexible substrate is fixed by the
rigid member in a condition that always maintains tensile distortion
within a temperature range from the room temperature to a testing
temperature. Therefore, when the probe card is heated in the test,
relaxation of tensile distortion is found and expansion in the flexible
substrate follows to expansion in the rigid member. Hence, when a
expansion rate of the rigid member is equal to that of the semiconductor
wafer, no dislocation occurs between the probe terminal and the integrated
circuit terminal of the semiconductor wafer to be tested even in the
periphery of the semiconductor wafer.
It is preferable in the first probe card that the rigid member has a first
terminal formed on one main surface of the rigid member and a wiring layer
electrically connected to the first terminal, the flexible substrate has a
second terminal formed on the other main surface thereof and electrically
connected to the probe terminal, and the flexible substrate is fixed to
the rigid member in such a manner that the first terminal confronts with
the second terminal and is electrically connected with each other.
With this arrangement, when the electric power voltage or signal is input
to the wiring layer of the rigid member, this electric power voltage or
s | | |
