Method and system for storing and processing multiple memory addresses

Claims

I claim:

1. A system for storing and processing a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address, the system comprising:

a command buffer receiving and storing a predetermined number of command words of each command packet;

at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer;

an address pipeline having an input bus coupled to the command word register, the address pipeline having an plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, each of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal;

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units; and

a memory address processing circuit coupled to the output bus of the address pipeline.

2. The storing and processing system of claim 1, wherein the memory address processing unit comprises an address decoder.

3. The storing and processing system of claim 1 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

4. The storing and processing system of claim 1 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

5. The storing and processing system of claim 4 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

6. The storing and processing system of claim 1, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

7. The storing and processing system of claim 1 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cell in at least one memory array.

8. A memory device, comprising:

at least one array of memory cells adapted to store data at a location determined by a row address and a column address;

a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit;

a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit;

a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively;

a command buffer adapted to receive a memory command to control the operation of the memory device;

an address buffer adapted to receive row addresses and column addresses applied to the address buffer;

an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal;

a memory address processing circuit coupled to the output bus of the address pipeline; and

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

9. The memory device of claim 8, wherein the memory address processing unit comprises an address decoder.

10. the memory device of claim 8 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

11. The memory device of claim 8 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

12. The memory device of claim 11 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

13. The memory device of claim 8, further comprising an adder for allowing the memory device to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

14. The memory device of claim 8 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in the array of memory cells.

15. A memory device, comprising:

at least one array of memory cells adapted to store data at a location determined by a tow address and a column address;

a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit;

a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit;

a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively;

a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address;

at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer;

an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, each of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal;

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units; and

a memory address processing circuit coupled to the output bus of the address pipeline.

16. The memory device of claim 15, wherein the memory address processing unit comprises an address decoder.

17. The memory device of claim 15 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

18. The memory device of claim 15 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuits.

19. The memory device of claim 18 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

20. The memory device of claim 15, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

21. The memory device of claim 15 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.

22. A computer system, comprising:

processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, comprising:

at least one array of memory cells adapted to store data at a location determined by a row address and a column address;

a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit;

a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit,

a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively;

a command buffer adapted to receive a memory command to control the operation of the memory device;

an address buffer adapted to receive row addresses and column addresses applied to the address buffer;

an address pipeline having an input bus coupled to the address buffer, and a plurality of address storage units each of which stores a respective address applied to the input bus responsive to a respective input enable signal, each of the address pipelines applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal;

a memory address processing circuit coupled to the output bus of the address pipeline; and

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

23. The computer system of claim 22, wherein the memory address processing unit comprises an address decoder.

24. The computer system of claim 22 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

25. The computer system of claim 22 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

26. The computer system of claim 25 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

27. The computer system of claim 22, further comprising an adder for allowing the memory device to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

28. The computer system of claim 22 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in the array of memory cells.

29. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, comprising:

at least one array of memory cells adapted to store data at a location determined by a row address and a column address;

a row address circuit adapted to select a row of memory cells in the array corresponding to a row address applied to the row address circuit;

a column address circuit adapted to select a column of memory cells in the array corresponding to a column address applied to the column address circuit;

a data path circuit adapted to couple data between an external terminal and a memory cell in the row and column of the array corresponding to the row and column address applied to the row address circuit and the column address circuit, respectively;

a command buffer adapted to receive a plurality of command packets each of which contain a plurality of command words, at least one of the command words containing at least one memory address;

at least one command word register coupled to the command buffer, the command words being transferred from the command buffer to the command word register after the predetermined number of command words have been stored in the command buffer;

an address pipeline having an input bus coupled to the command word register, the address pipeline having a plurality of address storage units each of which stores a respective memory address applied to the input bus responsive to a respective input enable signal, cach of the address storage units applying its stored address to an output bus of the address pipeline responsive to a respective output enable signal;

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units, and

a memory address processing circuit coupled to the output bus of the address pipeline.

30. The computer system of claim 29, wherein the memory address processing unit comprises an address decoder.

31. The computer system of claim 29 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

32. The computer system of claim 29 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

33. The computer system of claim 32 wherein the address bus circuits each comprises a latch having all input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

34. The computer system of claim 29, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

35. The computer system of claim 29 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.

36. A method of processing memory addresses in a memory device, comprising

applying a plurality of memory addresses to the memory device,

storing the memory addresses as they are received by the memory device so that a plurality of memory addresses may be simultaneously stored in the memory device; and

processing each of the stored memory addresses.

37. The method of claim 36 wherein the step of processing each of the stored memory addresses comprises selectively decoding each of the stored memory addresses.

38. The method of claim 36, further comprising the step of conveying the memory addresses over a common signal path from a location where the step of storing the memory address is performed to the location where the step of selectively processing each of the stored memory addresses is performed.

39. The method of claim 36 wherein the memory addresses comprise addresses designating a column of at least one array of memory cells.

40. The method of claim 36 further comprising latching each of the memory addresses one-at-a-time after the memory addresses have been stored in the memory device, and wherein the act of processing each of the stored memory addresses comprises processing each of the memory addresses after each of the memory addresses have been latched.

41. The method of claim 36 further comprising:

latching one of the memory addresses after the memory address has been stored in the memory device; and

sequentially incrementing the latched memory addresses to provide a plurality of memory addresses increasing in value from the latched memory address.

42. A method of storing and processing memory addresses embedded in respective packets, each packet containing M N-bit packet words, the method comprising:

sequentially receiving and storing each of the M packet words in a plurality of packets;

combining the M packet words in each packet into a corresponding M*N bit packet word;

storing a portion of each M*N bit packet word corresponding to the memory address for a plurality of packets so that a plurality of packet word portions corresponding to respective memory addresses may be simultaneously stored;

processing each of the packet word portions corresponding to respective memory addresses.

43. The method of claim 42 wherein the step of processing each of the packet word portions corresponding to respective memory addresses comprises selectively decoding each of the packet word portions.

44. The method of claim 42, further comprising the step of conveying the packet word portions over a common signal path from a location where the step of storing the packet word portions is performed to the location where the step of selectively processing each of the step of processing each of the packet word portions Is performed.

45. The method of claim 42 wherein the packet word portions comprises memory addresses designating a column of at least one array of memory cells.

46. The method of claim 42 further comprising latching each of the packet word portions one-at-a-time after the packet word portions have been stored, and wherein the act of processing each of the stored packet word portions comprises processing each of the packet word portions after each of the packet word portions have been latched.

47. The method of claim 42 further comprising:

latching one of the packet word portions after the packet word portion has been stored; and

sequentially incrementing the latched packet word portion to provide a plurality of memory addresses increasing in value from the memory address corresponding to the latched packet word portion.

48. A system for storing and processing memory address, comprising

an address pipeline having an input bus, an output bus, and a plurality of address storage units each of which stores a respective memory address, the address storage units each storing a memory address applied to the input bus responsive to a respective input enable signal and applying its stored address to the output bus responsive to a respective output enable signal;

a memory address processing circuit coupled to the output bus of the address pipeline; and

a control circuit selectively applying the respective input enable signals and output enable signals to each of the address storage units.

49. The storing and processing system of claim 48, wherein the memory address processing unit comprises an address decoder.

50. The storing and processing system of claim 48 further comprising a latch having an input bus coupled to the output bus of the address pipeline to receive each one of the memory addresses stored in the address storage units and an output bus coupled to the memory address processing circuit to process a memory address stored in the latch.

51. The storing and processing system of claim 48 further comprising a plurality of address bus circuits each of which is coupled to a respective bit of the output bus, the bus circuits coupling the memory address from an enabled address storage unit to the memory address processing circuit.

52. The storing and processing system of claim 51 wherein the address bus circuits each comprises a latch having an input coupled to a respective bit of the output bus and an output coupled to the memory address processing circuit.

53. The storing and processing system of claim 48, further comprising an adder for allowing the storing and processing system to operate in a burst mode, the adder having an input bus coupled to the output bus of the address pipeline and an output bus coupled to the memory address processing circuit, the adder generating a series of addresses that increment from an initial address stored in the address pipeline.

54. The storing and processing system of claim 48 wherein the memory addresses stored in each of the address storage units of the address pipeline comprise respective addresses of columns of memory cells in at least one memory array.

TECHNICAL FIELD

This invention relates to memory devices used in computer systems, and, more particularly, to a memory address register for storing multiple memory addresses for subsequent processing.

BACKGROUND OF THE INVENTION

Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories ("ROMs") which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory ("SRAM"). The processor also communicates with input devices, output devices, and data storage devices.

Processors generally operate at a relatively high speed. Processors such as the Pentium.RTM. and Pentium Pro.RTM. microprocessors are currently available that operate at clock speeds of at least 200 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 200 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.

Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 200 MHz to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.

System memory devices are generally dynamic random access memories ("DRAMs"). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories ("SDRAMs") have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.

A solution to this operating speed disparity has been proposed in the form of a computer architecture known as "SyncLink." In the SyncLink architecture, the system memory may be coupled to the processor directly through the processor bus, although it may also be coupled to the processor through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.

An example of a computer system 10 using a SyncLink packetized DRAM architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled to three memory devices 16a-c, such as packetized dynamic random access memory or SyncLink DRAMs ("SLDRAM") devices, either directly (as shown) or through a memory controller or the like (not shown). The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through a bus bridge 22 and an expansion bus 24, such as an industry standard architecture ("ISA") bus or a peripheral component interconnect ("PCI") bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 30 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.

In operation, the processor 12 communicates with the memory devices 16a-c via the processor bus 14 by sending the memory devices 16a-c command packets that contain both control and address information. Data is coupled between the processor 12 and the memory devices 16a-c through a data bus portion of the processor bus 14. Although all the memory devices 16a-c are coupled to the same conductors of the processor bus 14, only one memory device 16a-c at a time reads or writes data, thus avoiding bus contention on the processor bus 14. Bus contention is avoided by each of the memory devices 16a-c and the bus bridge 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.

The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16a-c also receive a master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device 16, and a FLAG signal signifying the start of a command packet.

One of the memory devices 16 is shown in block diagram form in FIG. 2. The memory device 16 includes a clock divider and delay circuit 40 that receives a master clock signal 42 and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16. The memory device 16 also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock CLK signal, a command packet CA0-CA9 on a command bus 50, and a FLAG signal on line 52. As explained above, the command packet contains control and address information for each memory transfer, and the FLAG signal identifies the start of a command packet. The command buffer 46 receives the command packet from the bus 50, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16 or some other memory device 16. If the command buffer 46 determines that the command is directed to the memory device 16a, it then provides the command to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16 during a memory transfer corresponding to the command.

The address capture circuit 48 also receives the command packet from the command bus 50 and outputs a 20-bit address corresponding to the address information in the command. The address is provided to an address sequencer 64 which generates a corresponding 3-bit bank address on bus 66, an 11-bit row address on bus 68, and a 6-bit column address on bus 70.

One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM device 16a shown in FIG. 2 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a memory read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receives a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time as determined by bank control logic 94 as a function of bank data from a bank address register 96.

The column address on bus 70 is applied to a column latch/decoder 100 which, in turn, supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense ampl