Process for manufacturing a semiconductor package with bi-substrate die

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FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and particularly to an improved method for forming an interconnect for electrically interconnecting semiconductor devices. The interconnect can be used to form an electrical connection to a memory cell array on a die, to form an electrical connection to a die having microscopic bond pads or to interconnect multiple dice contained on one or more wafers.

BACKGROUND OF THE INVENTION

As semiconductor manufacture advances to ultra large scale integration (ULSI), semiconductor devices continue to shrink in size. Circuit densities of several million transistors per die are now possible. As semiconductor devices shrink so does the die size. This has necessitated a reduction in bond pad sizes as well. It is anticipated that bond pads will soon be as small as 25 .mu.m.times.25 .mu.m on a side and spaced apart by only about 25 .mu.m. A thickness of the bond pad stack also continues to shrink so that bond pads as thin as 5000 .ANG. to 1 .mu.m are anticipated.

One problem with the shrinking dice and bond pads is that establishing an electrical connection to the bond pads is becoming more difficult. A preferred method of forming this electrical connection is by wire bonding. During a typical die packaging process, the bond pads formed on the face of the die are connected to a lead frame using fine bond wires. Typically, several dice are wire bonded to a single lead frame. The semiconductor dice are then encapsulated and a trim and form operation is used to separate the packaged dice and to bend the lead frame to form external leads in a desired configuration (e.g., J-bend, gull wing).

Apparatus for wire bonding semiconductor dice are well known in the art. Earlier versions of wire bonding apparatus were manually operated by an operator viewing the dice and bond pads through a microscope. More recently, automated wire bonding apparatus include vision systems for automatically sensing the locations of the bond pads on the dice and lead fingers of the leadframe to perform the wire bonding process. However, this technology is limited by the size and spacing of the bond pads which must be individually aligned and contacted by a wire bonding tool.

Another problem with current packaging technology is in the fixed relationship of the bond pads and interconnect circuitry on the die. For example, a conventional semiconductor DRAM die includes a memory cell array containing rows and columns of FETs associated with capacitors which store an electrical charge. The DRAM die also contains control and logic circuitry that interconnect to the memory cell array and terminate in the bond pads on the face of the die. The control and logic circuitry, which is typically on the periphery of the memory cell arrays, includes devices for addressing the array and for inputing and outputing data from the array. Typically the die is designed and constructed as a unitary structure containing both the memory cell array and the interconnect circuitry. The location of these components is fixed by the design and construction of the die.

In some applications it would be advantageous to be able to construct a die or a package in separate modules. For example, a memory cell array could be constructed as a component that is separate from the interconnect circuitry. This would allow a standard memory array to be provided but customized with different interconnect circuitry and bond pad arrangements for a particular application. Manufacturing costs could be reduced by the standardization and interchangeability of the different components. In addition, although contacts to the memory cells could remain small, the location and size of bond pads for connection to the outside could be made larger. This same scheme could be used to form a packaged die, to form an electrical connection to a die having microscopic bond pads, and to stack and interconnect dice contained on the wafers.

The present invention is directed to a method for forming an interconnect for semiconductor devices. The method can be used to form an electrical connection to microscopic contacts to semiconductor devices. In addition, the method can be used to form an electrical connection to microscopic bond pads for packaging a single die or multiple dice contained on a wafer.

Accordingly, it is an object of the present invention to provide an improved method for forming an interconnect for semiconductor devices.

It is a further object of the present invention to provide an improved semiconductor die having a separate interconnect substrate for making an electrical connection to memory devices contained in the die and for providing convenient sized and located bonds pads for connection to the outside.

It is a still further object of the present invention to provide an improved interconnect for making an electrical connection to microscopic bond pads on a semiconductor die.

It is yet another object of the present invention to provide an improved method for interconnecting multiple dice contained on a wafer and for interconnecting multiple wafers to one another.

Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method for forming an interconnect for making an electrical connection to semiconductor devices is provided. The interconnect includes raised contact structures for physically contacting and establishing an electrical connection to contacts in electrical communication with the semiconductor devices. These contacts on the die can include flat metallic bond pads, bond pads that are bumped with solder balls, and metal runners. The raised contact structures include one or more penetrating projections for piercing the contacts to the semiconductor devices to a limited penetration depth. In addition, each raised contact structure can be covered with a conductive layer that is bonded to a corresponding contact to the semiconductor devices.

The interconnect can be used to form a memory device such as a DRAM die out of two separate substrates rather than as a conventional monolithic structure. A first substrate, termed herein as a "memory substrate", contains the memory cell array for the DRAM. A second substrate, termed herein as an "interconnect substrate", contains control and logic circuitry, and bonding pads for connection to the outside world. The memory substrate and interconnect substrate are aligned and then placed into physical contact so that the penetrating projections on the raised contact structures penetrate the contacts on the memory substrate and establish a permanent electrical connection therebetween. The contact structures on the interconnect substrate and the contacts on the memory substrate are then bonded together.

The assembled memory substrate and interconnect substrate can be mechanically bonded together to make a permanent contact using a low temperature thermal process. This forms a bi-substrate die that can then be packaged in an encapsulating material. Advantageously, the contacts on the memory substrate can be small and dense thereby accommodating the size reductions in dense memory arrays. On the other hand, the bonding pads on the interconnect substrate can be relatively large to accommodate a subsequent wire bonding process and connection to the outside world. Another advantage is that manufacture of the bi-substrate die is simplified because a standardized memory substrate can be volume manufactured and combined with a customized interconnect substrate having a desired control and logic circuitry and a desired bonding pad configuration. Conversely the interconnect substrate can be standardized and the memory substrate customized.

Alternately the interconnect substrate does not need to include control and logic circuitry. In this case, the die could be a conventional monolithic structure having microscopic bond pads in electrical communication with the semiconductor devices and integrated circuits formed on the die. The interconnect substrate allows an electrical connection to be made to the microscopic bond pads on the die. This connection can be used for testing the die and for establishing a permanent electrical connection to the die.

An interconnect constructed in accordance with the invention can also be used to electrically connect extremely small and thin contact locations (e.g., metallic bond pads, metal runners, solder bumps) on a semiconductor die for testing or permanent use. In this case, the penetrating projections for the interconnect can be formed as three dimensional micro structures such as cylindrical tips adapted to penetrate into the contact locations on the die to a limited penetration depth. The micro structures can also be formed to engage a contact location on the die, such as a metal runner, that can bend or deform to a shape of the micro structure.

An interconnect constructed in accordance with the invention can also be used to electrically connect multiple semiconductor dice contained on a semiconductor wafer. This embodiment can be constructed to accommodate both regular sized bond pads and thin microscopic bond pads. In this embodiment the interconnect is wafer sized and includes raised contact structures having penetrating projections covered with a conductive layer. Two or more wafers can be stacked together and electrically connected using this type of wafer interconnect. Alternately, a wafer can be formed with the dice on a face of the wafer and raised contact structures on a backside of the wafer. Using this arrangement multiple wafers can be stacked together in electrical communication.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view of a memory substrate for a bi-substrate die constructed in accordance with the invention;

FIG. 1A is a schematic perspective view of a conventional monolithic die having microscopic bond pads;

FIG. 2 is a schematic perspective view of an interconnect substrate for constructing a bi-substrate die in accordance with the invention;

FIG. 3 is a schematic drawing showing an assembly sequence for constructing a bi-substrate die in accordance with the invention;

FIG. 4 is a schematic drawing of a bi-substrate die constructed in accordance with the invention;

FIG. 5 is a schematic drawing of a packaged bi-substrate die constructed in accordance with the invention;

FIG. 6 is a cross sectional view taken along section line 6--6 of FIG. 4 showing a contact structure on an interconnect engaging a contact on a memory substrate or die;

FIG. 6A is a perspective view of a contact structure for an interconnect constructed in accordance with the invention;

FIG. 7A is a schematic perspective view of a contact structure constructed in accordance with the invention with a three dimensional penetrating projection;

FIG. 7B is schematic perspective view of the contact structure shown in FIG. 7A engaging contacts on a semiconductor die;

FIG. 7C is a schematic side elevation view of another contact on a die formed as a metal runner and engaging a contact structure on an interconnect constructed in accordance with the invention;

FIGS. 8A and 8B are schematic side elevation views illustrating a contact structure constructed in accordance with the invention engaging a deformable contact formed on a die;

FIG. 9 is a perspective view of an alternate embodiment wafer interconnect constructed in accordance with the invention;

FIG. 10 is a schematic side elevation view of the wafer interconnect engaging a semiconductor wafer;

FIG. 11 is an enlarged schematic perspective view of the wafer interconnect showing contact structures formed thereon;

FIG. 12 is a schematic side elevation view showing multiple wafer interconnects and wafers stacked on one another to form a stacked array;

FIG. 12A is a schematic side elevation view of an alternate embodiment stacked array; and

FIG. 13 is a schematic cross sectional view of wafers formed with interconnects constructed in accordance with the invention on a backside and assembled together in a stacked array.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIGS. 1-3, the construction of a bi-substrate die in accordance with the invention is shown. A memory substrate 10 (FIG. 1) and an interconnect 12 substrate (FIG. 2) are used to construct the bi-substrate die 28 (FIG. 4). The memory substrate 10 includes a silicon substrate 14 wherein a memory cell array 16, represented by the cross hatched area, is constructed. The memory cell array 16 includes rows and columns of semiconductor devices such as FETs and capacitors constructed using techniques that are well known in the art. As an example, the semiconductor devices can be constructed as integrated circuits for a dynamic random access memory (DRAM)

The memory substrate 10 also includes a plurality of contacts 18 in electrical communication with the semiconductor devices formed in the memory cell array 16. The contacts 18 are preferably metallic pads formed of a material such as aluminum or another highly conductive metal. The contacts 18 are equivalent to bond pads on a conventional die but can be made much smaller and thinner than conventional bond pads. By way of example, the contacts 18 can be polygonal in shape, about 10-25 .mu.m on a side, and with a thickness of from about 1000 .ANG. to 1.0 .mu.m. In the embodiment shown in FIG. 1, the contacts 18 are arranged in pairs in a cross shaped pattern. This pattern, however, as well as the cited size range, are merely exemplary.

The memory substrate 10 is adapted for mating engagement with the interconnect substrate 12 shown in FIG. 2. As shown in FIG. 3, during an assembly process the memory substrate 10 is flipped face down, aligned with the interconnect substrate 12 and then brought into physical contact with the interconnect substrate 12.

The interconnect substrate 12 includes a silicon substrate 22 and a plurality of raised contact structures 20 which correspond to the location of the contacts 18 on the memory substrate 10. The construction of the raised contact structures 20 will become more apparent as the description proceeds. The interconnect substrate 12 also includes control and logic circuitry 24 formed in the silicon substrate 22. The control and logic circuitry 24 includes various semiconductor devices formed or mounted on the silicon substrate 22 using techniques that are known in the art. The control and logic circuitry 24 is adapted to access and control the semiconductor devices formed in the memory cell array 16 of the memory substrate 10.

The raised contact structures 20 on the interconnect substrate 12 are in electrical communication with the control and logic circuitry 24. The raised contact structures 20 are also in electrical communication with bonding pads 26. The bonding pads 26 can be formed with a relatively large size (e.g., 100 .mu.m.times.100 .mu.m) to facilitate a subsequent wire bonding process. In addition, the bonding pads 26 are spaced in a desired pattern along the sides of the interconnect substrate 12. The bonding pads 26 can be formed of a material such as aluminum alloyed with other metals useful in pad metallurgy. As shown in FIG. 4, following assembly of the die 28 thin bond wires 30 are wire bonded to the bonding pads 26 on the interconnect substrate 12. The peripheral shape of the interconnect substrate 12 can be larger than that of the memory substrate 10 so that in the assembled die 28 the bonding pads 30 are exposed for wire bonding.

Wire bonding can be effected using a wire bonder apparatus and conventional semiconductor wire bonding techniques (e.g., gold ball thermosonic, aluminum wedge). One suitable wire bonding apparatus for performing the wire bonding step is manufactured by Kulicke and Soffa, Horsham, Pa. and is designated as a K&S Model 1484. Although wire bonding is the preferred method of forming an electrical connection to the bonding pads 26, a soldered connection can also be employed. In addition, a mechanical electrical connection 30M (FIG. 6) such as a sliding or piercing structure could also be employed.

Referring now to FIG. 6, the construction of the contact structure 20 and its function in establishing an electrical connection with a contact 18 on the memory substrate 10 are shown. The contact structure 20 is a raised member formed integrally with the silicon substrate 22 for the interconnect 12 preferably by etching the silicon substrate 22. The contact structure 20 includes penetrating projections 32 that are designed to penetrate into the contacts 18 on the memory substrate 10 to a limited penetration depth. The designed penetration depth can also be a function of the thickness of the contact 18. The contact structure 20 also includes a conductive layer 34 formed atop the penetrating projections 32. The conductive layer 34 is insulated from the silicon substrate 22 by an insulating layer 36. In addition, the conductive layer 34 is in electrical communication with conductive traces 38 formed on the silicon substrate 22 in electrical communication with the bonding pads 26. The conductive layer 34 is also in electrical communication with the control and logic circuitry 24 (FIG. 2). As shown in FIG. 2, the conductive traces 38 establish an electrical connection between the contact structures 20 and the bonding pads 26 and an electrical connection between the contact structures 20, the contacts 18 and the control and logic circuitry 24.

The contact structure 20 can be formed using an etch process. Such an etch process is described in copending, commonly assigned U.S. Pat. No. 5,686,307 and in U.S. Pat. No. 5,326,428 and U.S. Pat. No. 5,419,807 which are incorporated herein by reference.

Still referring to FIG. 6, for fabricating the contact structures 20, initially the penetrating projections 32 are formed using an etch mask (not shown). The etch mask can be formed out of a material such as silicon nitride (Si.sub.3 N.sub.4) by blanket depositing the material (e.g., CVD) followed by photopatterning and then etching (e.g., wet or dry etch). Using the etch mask the exposed silicon substrate 22 is etched to form the penetrating projections 32. In this step a wet or dry isotropic, or anisotropic, etch process is used to form the projections 32. For an anisotropic etch, in which the etch rate is different in different single crystal directions, an etchant solution containing a mixture of KOH and H.sub.2 O can be utilized. This results in the penetrating projections 32 being formed with sidewalls that are sloped at an angle of approximately 54.degree. with the horizontal. In addition, depending on the size of the etch mask, the penetrating projections can be formed as elongated blades as shown in FIG. 6A or miniature pyramids.

In place of an anisotropic etch, an isotropic etch can be used to form the penetrating projections 32 with radiused sidewalls or a rounded profile (not shown). For an isotropic etch in which the etch rate is the same in all directions, an etchant solution containing a mixture of HF, HNO.sub.3 and H.sub.2 O can be utilized. This will result in the projections 32 having a pointed tip and a radiused sidewall contour (not shown).

The placement and peripheral dimensions of the penetrating projections 32 corresponds to the placement and peripheral dimensions of the contacts 18 formed on the memory substrate 10. The height of each projection 32 is preferably about 1/10 to 3/4 the thickness of the metal layer that forms the contacts 18. The projections 32 will therefore not completely penetrate the full thickness of the contacts 18 and an upper surface 40 of the contact structure 20 provides a stop plane for limiting further penetration of the projections 32 into the contact 18. In addition, the height of the projections 32 is selected to allow good electrical contact. As an example, the height of each penetrating projection 32 measured from the upper surface 40 of the silicon substrate 22 to the tip of the projection 32 will be on the order of 500 .ANG.-1 .mu.m. Example spacing between the projections 32 would be about 5 .mu.m, while a length of the projections 30 (i.e., dimension perpendicular to the cross section shown) would be dependent on the size of t