Process for fabricating semiconductor device having semiconductor layers epitaxially grown from active areas without short-circuit on field insulating layer
A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.
In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.
According to one example method of fabricating a semiconductor memory device, an isolation layer and a capping layer are formed on a silicon substrate, sequentially. By an epitaxial silicon growth process, an epitaxial active region is formed. A gate insulation layer and a gate electrode are then formed on the epitaxial active region, sequentially. Subsequently, a bit line contact plug and a storage node contact plug are epitaxially formed on the epitaxial active region. A lower interlayer insulation layer is formed on the resultant structure and planarized. An upper interlayer insulation layer is formed on the lower interlayer insulation layer and a bit line is formed therein. An additional upper interlayer insulation layer is then formed on the entire surface of the resultant structure and a storage node electrode is formed through the additional upper and the upper interlayer insulation layer to be connected to the storage node contact.
A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.
