Contacts for an electronic device are formed by providing a substrate (12) that has at least two access line structures (16) for a memory array (14) and a periphery structure (20) for a peripheral circuit (18) to the memory array (14). A first insulative layer (40) is formed outwardly of the substrate (12), the access line structures (16), and the periphery structure (20). A contact area of the periphery structure (20) is exposed through the first insulative layer (40) while maintaining the first insulative layer (40) over at least a contact overlap portion (48) of the access line structures (16). A second insulative layer (60) is formed outwardly of the substrate (12), the access line structures (16), the periphery structure (20), and the first insulative layer (40). A self-aligned contact hole (70) overlapping the contact overlap portion (48) of the access line structures (16) and a periphery contact hole (72) overlapping the contact area (46) of the periphery structure (20) are formed through the second insulative layer (60) with a same mask (74). A self-aligned contact (80) is formed in the self-aligned contact hole (70) and a periphery contact (82) is formed in the periphery contact hole (72).

A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.