An oscillation stop detection circuit comprises delay means for delaying an oscillation signal having a predetermined cycle by a predetermined time to thereby output a delayed signal therefrom, detecting means for exclusive-ORing the oscillation signal and the delayed signal to thereby detect the presence of the oscillation signal and outputting a pulse signal in the predetermined cycle when the oscillation signal exists, and charge and discharge means having a capacitor electrically connected between an output node for outputting a detection signal indicative of whether the oscillation signal is at a stop and a source potential or a ground potential, and for discharging the capacitor when the pulse signal is supplied and charging the capacitor according to a predetermined time constant while the pulse signal is unsupplied.

Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.

A semiconductor device includes an external resistor for establishing a delay of a signal relative to another signal in the device. The resistor may be external to a buffer, such as a zero-delay buffer, that receives an input signal generates one or more output signals that relate to the input signal. The delay may be introduced either before or after the buffer.

An input buffer circuit includes an input buffer. The input buffer has an input adapted to be coupled to an address bus and a power down input. The input buffer circuit further includes power down circuitry adapted to be coupled to an address bus strobe and coupled to the power down input. When the address bus is detected to be idle by the power down circuitry, a power down signal is sent to the power down input. This powers down the input buffer.