A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.
A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.
An apparatus comprising a first circuit configured to present one or more control indication signals and (ii) a control clock signal in response to (i) one or more select signals, (ii) one or more clock signals and (iii) one or more divider control signals. The first circuit may be configured to select an active channel from a plurality of channels in response to the one or more select signals.
An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a plurality of control signals and a select signal, in response to (i) a receive clock signal, (ii) a reference clock signal and (iii) a master clock signal. The second circuit may be configured to generate a read signal and a window signal in response to the plurality of control signals. The third circuit may be configured to generate a lock signal in response to (i) the reference clock signal, (ii) the select signal, (iii) the read signal and (iv) the window signal. The receive clock signal and the reference clock signal may be independent clocks configured to provide range control over one or more channels.
Ripple counter circuits in integrated circuit devices can have fast terminal count capability. A terminal count circuit can be configured to mask selected unstable counter bits generated by a ripple counter circuit using an indication that a terminal state of the ripple counter circuit has been reached. Related methods are also disclosed.
In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and utilizing the first and second beat signals to determine if a lock condition has occurred. A system and method in accordance with the present invention indicates a lock to the desired reference clock and provides an error or out of lock condition if the recovered frequency is at a harmonic or subharmonic of the reference frequency. This ability to avoid a false lock indication requires very little additional circuitry. A further improvement is that the circuit correctly indicates out of lock condition even in the absence of a reference frequency, caused for instance by a broken signal connection.
