An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.
According to one embodiment, an integrated circuit is disclosed that includes a first input/output (I/O) circuit and a leakage detection circuit coupled to the first I/O circuit. In a test mode of operation, the leakage detection circuit tests the first I/O circuit for excessive leakage current. According to another embodiment, the integrated circuit also includes a first resistor coupled between a line voltage and the first I/O circuit and a second resistor coupled between the first I/O circuit and ground. Further, the integrated circuit includes a second I/O circuit coupled to the leakage detection circuit and the first and second resistors. The leakage circuit also tests the second I/O circuit for excessive leakage current in the test mode of operation.
A method of fabricating an HV-I/O ESD MOS device comprising the following steps. A structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region. An HV-LDD implant is performed into the structure adjacent the second device gate and the HV-I/O ESD MOS device gate to form second device HV-LDD implants and HV-I/O ESD MOS device HV-LDD implants. The HV-LDD mask is removed. Spacers are formed over the respective exposed side walls of the gate and oxide layers within each respective region to complete fabrication of a first device, a second device and the HV-I/O ESD MOS device. In an alternate embodiment, an I/O LV device may also be simultaneously formed within an I/O LV device region.
A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V.sub.ss) and/or V.sub.cc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n.sup.+ -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n.sup.+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.
