Suppression of boron segregation for shallow source and drain junctions in semiconductors

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TECHNICAL FIELD

The present invention relates generally to semiconductor manufacturing technology and more specifically to deep-submicron P-channel Metal-Oxide Semiconductor (MOS) transistor manufacturing.

BACKGROUND ART

Deep-submicron Complementary Metal-Oxide-Semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) circuits. Scaling of CMOS has been the principal focus of the microelectronics industry over the last two decades. As device sizes are scaled down, the source and drain junctions have to scale down accordingly to suppress the so-called short channel effects (SCE) which degrade the performance of scaled MOS devices. A major problem related to source and drain junctions is that the source and drain series resistance increases as the devices are scaled down, which degrade the device performance.

Advanced MOS transistors today have shallow source and drain junctions, which consist of shallow source and drain extension junctions to suppress SCE, and relatively deep source and drain junctions to improve series resistance. The resistance from shallow source and drain extension junctions is a large portion of the total series resistance. As extension junctions become shallower and shallower, the series resistance tends to become greater and greater. In order to make the source and drain series resistance low, high doping density is needed in the shallow extension junctions.

Generally, the shallow source and drain extension junctions and the relatively deep source and drain junctions are implemented by ion implantation of dopant through a screen oxide (Si0.sub.2) layer. Implantation through an oxide layer results in the deposition of recoiled oxygen into the silicon. This oxygen has a tendency to reduce the interstitial silicon which is present in the implant-damaged substrate. This, in turn, suppresses the diffusion tail associated with the implanted dopant, which moves by an interstitialcy mechanism. This increases the series resistance.

For N-channel Metal-Oxide-Semiconductor (NMOS) transistors, Group V elements are used as dopants.

For P-channel Metal-Oxide-Semiconductor (PMOS) transistors, Group III elements are used, with boron (B) being the most commonly used dopant for both the shallow extension junctions and the relatively deep source and drain junctions. Boron is incorporated into the silicon through ion implantation of either boron atoms or boron difluoride (BF.sub.2).

After ion implantation, the dopants need to be activated by a thermal treatment-usually a rapid thermal annealing (RTA). This causes a significant problem in that boron atoms tend to segregate from the silicon substrate into the screen oxide layer during the RTA of dopant activation. Boron segregation results in a decrease of boron concentration in the silicon substrate near its surface and therefore an increase of source and drain series resistance. This effect becomes more and more of a problem as device sizes are continuously scaled down and the extension and junction depths becomes shallower and shallower.

DISCLOSURE OF THE INVENTION

The present invention overcomes the problem that dopant atoms tend to segregate from silicon substrate into the screen oxide layer during the RTA of dopant activation by nitridizing the screen oxide layer into the oxynitride before the implantation of the dopant.

The present invention has the advantage of suppressing boron loss in silicon through segregation into the screen oxide layer during the boron activation RTA.

The present invention also has the advantage of providing advanced, deep submicron CMOS devices with overall ultra-shallow junctions which have low series resistance.

The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a semiconductor transistor gate area;

FIG. 2 is the semiconductor of FIG. 1 after screen oxide layer deposition;

FIG. 3 is the semiconductor of FIG. 2 after screen oxide layer nitridation;

FIG. 4 is the semiconductor of FIG. 3 during shallow source and drain extension junction implantation;

FIG. 5 is the semiconductor of FIG. 4 after conformal oxide layer deposition;

FIG. 6 is the semiconductor of FIG. 5 after spacer etching;

FIG. 7 is the semiconductor of FIG. 6 after screen oxide layer deposition;

FIG. 8 is the semiconductor of FIG. 7 after screen oxide layer nitridation;

FIG. 9 is the semiconductor of FIG. 8 during deep source and drain junction implantation;

FIG. 10 is the semiconductor of FIG. 9 after rapid thermal annealing; and

FIG. 11 is the semiconductor of FIG. 10 after removal of the screen oxynitride layer.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1, therein is shown a cross-section of a partially processed semiconductor wafer. The semiconductor wafer has been processed to the point at which a silicon substrate 10 has a silicon dioxide (SiO.sub.2) gate oxide layer 12 deposited on top. On top of the gate oxide layer 12 is a polysilicon (polycrystalline silicon) gate 14. The polysilicon gate 14 is positioned over an area or well of N.sup.- silicon. There are a number of different processing steps well known to those skilled in the art for arriving at the structure shown in FIG. 1.

Referring now to FIG. 2, therein is shown the silicon substrate 10 and the polysilicon gate 14 having a screen oxide layer 16 of silicon dioxide deposited thereon.

Referring now to FIG. 3, therein is shown a screen oxynitride layer 18 after nitridation which converts the silicon dioxide of the screen oxide layer 16 of FIG. 2 into a silicon oxynitride.

Referring now to FIG. 4, therein is shown the boron implantation 19 of the silicon substrate 10 to form the initial ultra-shallow, P-silicon source and drain junctions in the well of N.sup.- silicon. These initial junctions are designated as source and drain extension junctions 20 and 22. They are formed by ion implantation through the screen oxynitride layer 18.

Referring now to FIG. 5, therein is shown a conformal oxide layer 24 deposited on the screen oxynitride layer 18.

Referring now to FIG. 6, therein is shown the conformal oxide layer 24 and the screen oxynitride layer 18 after etching to form sidewall spacers and to expose the polysilicon gate 14 and the source and drain extension junctions 20 and 22.

Referring now to FIG. 7, therein is shown another, second screen oxide layer 26 deposited over the semiconductor wafer to cover the polysilicon gate 14 and the source and drain extension junctions 20 and 22.

Referring now to FIG. 8, therein is shown a second screen oxynitride layer 28 after nitridation which converts the silicon dioxide of the screen oxide layer 26 of FIG. 7 into silicon oxynitride.

Referring now to FIG. 9, therein is shown another, second boron implantation 29 of the silicon substrate 10 to form the relatively deep P-silicon source and drain junctions in the well of N.sup.- silicon. These junctions are designated as source and drain junctions 30 and 32, respectively, and are integral with the source and drain extension junctions 20 and 22. The source and drain junctions 30 and 32 are formed by ion implantation through the screen oxynitride layer 28.

Referring now to FIG. 10, therein is shown the deep-submicron CMOS transistor after the rapid thermal annealing for boron activation.

Referring now to FIG. 11, therein is shown the second screen oxynitride layer 28 etched away and the transistor ready for the remaining conventional processing. The remaining conventional processing would be evident to those skilled in the art as required to produce finished deep submicron (sub-0.1 micron) ultra large scale integrated (ULSI) circuit devices.

The process flow for the present invention starts with the silicon substrate 10 having been processed with wells of N.sup.- silicon and the deposition of the silicon dioxide gate oxide layer 12 and the polysilicon gate 14. The screen oxide layer 16 of silicon dioxide is then deposited as shown in FIG. 2, generally by low pressure chemical vapor deposition (LPCVD).

Next, a nitridation of the screen oxide layer 16 is performed. The nitridation is a rapid thermal annealing process in a gaseous nitrogen compound ambient. The rapid thermal annealing temperature would be around 900.degree. C. for 30 seconds. The gaseous nitrogen compounds include ammonia (NH.sub.3), nitric oxide (NO), and nitrous oxide (N.sub.2 O). Furnace annealing can also be used, but rapid thermal annealing is preferred for less doping redistribution. Furthermore, ammonia and nitric oxide rapid thermal annealing in particular are preferred, because they can incorporate more nitrogen into the screen oxide layer 16 with a peak near the interface with the silicon substrate 10.

As the result of the nitridation, the pure oxide of the screen oxide layer 16 will be turned into an oxynitride to form the screen oxynitride layer 18, as shown in FIG. 3. The fundamental principle is that nitrogen in oxides can significantly suppress boron diffusion and segregation into the oxides.

After the nitridation process, a dopant is implanted through the screen oxynitride layer 18 into the silicon substrate 10 to form the ultra-shallow, P-silicon source and drain extension junctions 20 and 22, as shown in FIG. 4. The conduction-increasing boron (B) dopant for P-silicon formation is ion implanted as elemental boron or as boron difluoride (BF.sub.2). The screen oxynitride layer 18, as previously explained, prevents the boron dopant from segregating from the silicon substrate 10 and maintains a high boron concentration in the silicon substrate 10 during the later rapid thermal anneals.

Next, the conformal oxide layer 24 is deposited over the screen oxynitride layer 18, as shown in FIG. 5. The conformal oxide layer 24 and the screen oxynitride layer 18 are then subject to an anisotropic reactive ion etch (RIE) process to arrive at the configuration shown in FIG. 6. The anisotropic etch uses the silicon of the silicon substrate 10 and of the polysilicon gate 14 as etch stops, and the etching continues until the silicon is exposed. This leaves the conformal oxide layer 24 as oxide spacers 24 against the oxynitride on the sides of and around the polysilicon gate 14.

Another second screen oxide layer 26 is then deposited again by LPCVD over the wafer, as shown in FIG. 7, and another nitridation is performed. The conditions of this second nitridation would be the same as previously described for the first nitridation step. Again, this turns the pure oxide in the screen oxide layer 26 of FIG. 7 into oxynitride to form the second screen oxynitride layer 28, as shown in FIG. 8.

Again, boron (B) or boron difluoride (BF.sub.2) is ion implanted through the screen oxynitride layer 28 into the silicon substrate 10 as shown in FIG. 9. This time, the implantation of the source and drain junctions 30 and 32 proceeds to create relatively deep junctions as compared to the ultra-shallow extension junctions 20 and 22. The oxide layer 24 absorbs the boron near the polysilicon gate 14 and prevents the shallow extension junctions 20 and 22 from getting significantly deeper.

A final rapid thermal anneal of the present invention is performed in a gaseous nitrogen (N.sub.2) atmosphere for activation of the boron in the silicon substrate 10, as shown in FIG. 10. Typical conditions are a temperature of about 1050.degree. C. and a time of about 30 seconds. Because of the screen oxynitride layer 28 on the surface of silicon substrate 10 in the boron implanted region, the segregation of boron from these implanted regions will be significantly suppressed or even totally stopped. This boron retention will improve the conductivity of the implanted region consisting of the source and drain extension junctions and junctions 20, 22, 30, and 32. This reduces the series resistance and increases the drive current of ULSI circuit devices.

A removal of the screen oxynitride layer 28 is carried out after the above final rapid thermal anneal by conventional wet etching to arrive at the configuration shown in FIG. 11. After this step, process flow of the ULSI device fabrication is conventional.

This process flow is totally compatible with the current CMOS technology and requires only very minor, but elegant, changes to the current CMOS technology. Only two additional nitridation steps are needed in the current CMOS process flow and each nitridation is a simple RTA in an ambient of NH.sub.3, NO, or N.sub.2 O.

While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

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