A Cache Memory Controller which operates in conjunction with a TAG Random Access Memory (TAG RAM) coupled to the lower order bits on a host address bus is provided. The Cache Memory Controller selects the data to be written to TAG RAM from two or more sources. One of these sources provides snoop address signals and another provides invalidating signals. During a read operation, the lower order bits of the address on the address bus address the TAG RAM while the n higher order bits are passed to a shifter and to a compare circuit. In response to the lower order bits of the address provided, the TAG RAM generates an n-bit TAG data output signal. If this data output compares exactly with the n higher order bits on the host address bus, the compare circuit will indicate a hit. If the compare circuit does not indicate a hit, the n higher order address bits are written into the TAG RAM. Data from main memory is then loaded into the cache memory. During a write operation, the lower order bits address the TAG RAM, with the n higher order being passed to the shifter as before. Upon the occurrence of a TAG write enable signal, the output of the shifter is written into the TAG RAM as data at the TAG RAM address corresponding to the address on the lower order address lines of the host bus. Data is then loaded from main memory into the cache memory.
A device, method and computer program for communicating between a device controller and an industry standard bus. This device method and computer program requires no modification of the core logic of the device driver even though the data and commands transmitted between the device controller and the bus require a different format and different length commands. This device utilizes a convert and store logic unit to convert commands from the core unit to a reduced bit format suitable for the industry standard bus.
A cache controller unit includes an address comparator unit for comparing an address to be accessed in memory with a tag address. An invalid pattern comparator is coupled to the address comparator. The invalid pattern comparator operates to compare the tag address with an invalid pattern. A qualifier unit is coupled to the address comparator and the invalid pattern comparator. The qualifier unit outputs a signal when the address to be accessed in the memory matches the tag address in the address tag and the address tag does not match the invalid pattern.
A data replication system is disclosed in which replication functionalities between a host computer, an interconnecting computer network, and a plurality of storage devices are separated into host elements and a plurality of storage elements. The host computer is connected to one or more host elements. The host element is responsible for replicating data between the storage devices, which are each connected to an associated storage element, and for maintaining data consistency. Further, the host element instructs a storage element whose associated storage device does not contain up-to-date data to recover from another one of the plurality of storage elements and its associated storage device. The storage elements and their associated storage devices may be located in any combination of diverse or same geographical sites in a manner to ensure sufficient replication in the event of a site or equipment failure. The storage elements are responsible for executing read and write requests received from the host computer and for maintaining data consistency. When a storage element and its associated storage device is determined not to contain up-to-date data, recovery is effected by data transfer from one of the other storage elements and its associated storage device, that is indicated by the host element. Such recovery is done directly between the respective storage elements and associated storage devices, without transiting the data through the host element.
