Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps

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FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture, and more particularly to an improved interconnect, system and method for testing semiconductor dice and packages having contact bumps.

BACKGROUND OF THE INVENTION

One type of semiconductor die, referred to as a "bumped" die includes patterns of contact bumps formed on a face of the die. The contact bumps can be formed on wettable metal contacts on the die in electrical communication with the integrated circuits contained on the die. The contact bumps allow the die to be "flip chip" mounted to a substrate having corresponding solder wettable contacts. This mounting process was originally developed by IBM and is also known as the C4 joining process (Controlled Collapse Chip Connection).

Lead tin alloys (e.g., 95/5 lead tin alloy) and a ball limiting metallurgy (BLM) process can be used to form the bumps. Typically, the bumps are dome shaped, and have an average diameter of from 5 mils to 30 mils. Micro ball grid arrays (BGA) are formed in the smaller range, while standard ball grid arrays are formed in the larger size range. The sides of the bumps typically bow or curve outwardly from flat top surfaces. The flat top surfaces of the bumps form the actual regions of contact with the mating contacts on the substrate.

Contact bumps are also sometimes included in chip scale packages. In general, a "chip scale package" or "chip size package" refers to a package that includes a bare die along with one or more packaging elements. For example, chip scale packages can include thin protective members attached to the face, sides or backside of the die. In addition, chip scale packages can include contact bumps similar to the bumps on bumped dice. Some persons skilled in the art consider a bumped die the simplest form of a chip scale package.

With bumped dice and chip scale packages, it is sometimes necessary to make non-bonded, or temporary, electrical connections with the contact bumps. For example, in the production of Known Good Die (KGD), semiconductor manufacturers are required to test bumped dice prior to shipment. Temporary packages can be used to house a single bare die, or a chip scale package, for burn-in and other test procedure. These types of temporary packages are disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.

Interconnects associated with the temporary packages can be used to electrically contact the bumps on the dice, or on the chip scale packages. With one type of interconnect, indentations on the interconnect can be sized to retain and electrically contact the bumps. For example, this type of interconnect can include a multi layered tape, similar to TAB tape manufactured by Nitto Denko and others. The tape can include a polyimide layer formed with patterns of indentations, and a metal layer subjacent to the indentations. The bumps fit into the indentations and electrically contact the metal layer.

To assist in making this temporary electrical connection, a temporary package can also include a force applying mechanism, such as a spring, adapted to bias the semiconductor component against the interconnect. A contact force must be generated by the force applying mechanism that is sufficient to break through the native oxide covering the bumps. If a sufficient contact force is not generated, then the resultant electrical connection can be poor. However, it is also advantageous to maintain this contact force as low as possible to avoid excessive deformation of the bumps. In particular, the loaded bumps exhibit creep during the burn-in cycles, which are typically performed at elevated temperatures for several hours or more.

In the past, following testing of dice with contact bumps, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step which adds to the expense and complexity of the testing process. Furthermore, it requires heating the tested dice which can adversely affect the integrated circuitry formed thereon.

Another consideration in testing bumped dice and chip scale packages is the dimensional variations between the contact bumps. The interconnect must be able to accommodate dimensional variations between bumps on different dice or packages, and dimensional variations between individual bumps on the same die or package. These dimensional variations can include the diameter, height, shape, and location of the bumps. In particular, the diameter and z-dimension location (planarity) of the bumps can make the electrical connections difficult to make without high contact forces.

Trapped gases can also cause problems during a reflow procedure. For example, gases can be trapped in cavities formed within the bumps. These trapped gas can expand during a reflow connection process causing the solder material to splatter.

In view of the foregoing, improved interconnects for making electrical connections to semiconductor dice and packages having contact bumps are needed. The present invention is directed to an improved interconnect able to provide a reliable electrical connection with the smallest contact bumps, while minimizing the deformation of the average and large sized contact bumps.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect adapted to establish temporary electrical communication with semiconductor components having contact bumps is provided. The semiconductor components can be bare bumped dice, bumped dice contained on a semiconductor wafer, or dice contained in chip scale packages having contact bumps. Also provided are a test system, and a testing method including the interconnect.

The interconnect includes a substrate having contact members for receiving and electrically contacting the contact bumps. Each contact member comprises a recess plated with a conductive layer in electrical communication with a corresponding conductor on the substrate. A peripheral edge of each recess is configured to penetrate into a contact bump retained in the recess, and to break through native oxide layers on the bump. In addition, the recesses can be shaped and dimensioned to contact the smallest bumps, as well as the largest bumps, with an acceptable amount of bump deformation. The dimensions of the recesses can be ascertained using statistical analysis of conventional bumps. In addition, the recesses can be formed with an elongated rectangular shape to permit the peripheral edges of the recesses to contact the bumps along a first axis (e.g., lateral axis) while permitting the bumps to flow along a second axis (e.g., longitudinal axis).

In an alternate embodiment, the contact members include blades projecting from the sidewalls of the recesses in a desired pattern (e.g., cross pattern, spoke pattern). The blades are shaped and dimensioned to penetrate only a portion of the bumps. This helps to minimize bump deformation and cavity formation in the bumps while forming reliable areas of electrical contact with the bumps. The recesses and blades can be formed with angled surfaces using an anisotropic etch process, or with rounded surfaces using an isotropic etch process. In addition, the blades can be contoured to match the topography of the contact bumps. This insures that the blades only minimally penetrate and deform the bumps.

The interconnect can be included in a wafer level test system, or a die level test system. In the wafer level test system, the interconnect can be mounted to a probe card fixture of a conventional testing apparatus, such as a wafer handler. During a test procedure, test circuitry associated with the testing apparatus can apply test signals through the interconnect to the integrated circuits on the dice. In addition, the test signals can be electronically switched as required to selected dice on the wafer. In the die level test system, the interconnect can be mounted to a temporary package configured to house a single bare die or a chip scale package. T