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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to personal computer systems and, more particularly, to a personal computer having security features enabling control over access to data retained in the computer.
2. Description of the Related Art
The rapid development and adaptation of new technology in the computer industry has enabled personal computers and peripherals to become ever more powerful and sophisticated. However, the torrid pace of technological innovation has rendered many
otherwise operable personal computers obsolete due to outdated system software. Particularly, if the system resident code (or firmware) is outdated, an IBM compatible computer may not be able to support features available with the latest peripherals.
Developed since the earliest generation of personal computers, the firmware residing in read only memory (ROM) provides an operational interface between a user's application program/operating system and the device to relieve the user of the
concern about specific characteristics of hardware devices. This insulation layer of code eventually evolved into a Basic Input/Output System (BIOS) code which allowed new devices to be added to the system while isolating the application program from
the peculiarities of the hardware. Since the BIOS is an integral part of the system and controls the movement of data in and out of the system processor, it resides on the system ROM. As new models of the personal computer family are introduced, the
BIOS had to be updated and expanded to include new hardware and I/O devices.
Since the technology is rapidly changing and new I/O devices are being added to the personal computer systems, modification to the BIOS and other system software is desirable to keep existing personal computers up to date to support the latest
peripherals while maintaining compatibility with existing peripherals. The availability of flash ROMs has made possible the ability to update the contents of the ROM without ever physically removing the ROM. However, since the BIOS is an integral part
of the operating system, a corrupt BIOS could lead to devastating results and in many cases to complete failure and non-operation of the system.
The user's awareness of accidental or intentional misuse or otherwise unauthorized modifications to the computer's system software has been made more acute following the publicity on the adverse consequences of computer security breaches. Thus,
security conscious users are requesting that security and integrity features be incorporated into their personal computers to protect the flash ROM and to prevent unintentional or malicious erasure of the flash ROM contents.
In previous systems, a switch was used to control the updating of the flash ROM. However, the switch method was burdensome and inflexible. A password approach is desirable due to lower cost of eliminating a switch, increased flexibility because
passwords can be easily changed, and enhanced user convenience while still providing the necessary level of security. But at the same time, the password approach must be sufficiently secure so that the password cannot be obtained during the process.
Thus, a security device is needed that can verify a password provided by the user instead of requiring the user to throw a switch to update the flash ROM and to perform such verification in a secure manner.
SUMMARY OF THE INVENTION
A computer according to the present invention provides security by having the system ROM provide a password at power-on to a security device which controls access to the secured features. Once a password has been downloaded to the security
device, a Protect Resources command is issued to the security device which controls access to the protected resources such as the flash ROM. To access the secured resource, the user provides the correct password to the security device. The security
device can only verify and not divulge the password, so security of the system is enhanced.
These and other features of the present invention will be understood upon reading of the following description along with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
FIG. 1 is a block diagram of a computer system according to the present invention;
FIG. 2 is flow diagram of the security management system in accordance with the present invention;
FIG. 3 is a state machine of the security management system used in implementing the flow diagram of FIG. 2;
FIGS. 4, 5 and 6 are schematic diagrams of portions of the security management system associated with the state machine of FIG. 4;
FIG. 7 is a schematic diagram of the flash ROM programming circuit;
FIG. 8 is a flow chart of the boot-up process of the computer of FIG. 1;
FIG. 9 is a flow chart of the BIOS software handler for the security management system in accordance with the invention;
FIG. 10 is a flow chart of BIOS initialization of the security management system in accordance with the invention;
FIG. 11 is a flow chart of the BIOS software handler for the permanent lock command of FIG. 10;
FIG. 12 is a flow chart of the BIOS software handler for the protect resources command of FIG. 10;
FIG. 13 is a flow chart of the BIOS software handler for the access resources command of FIG. 10;
FIG. 14 is a flow chart of the BIOS software handler for the read status command of FIG. 10; and
FIG. 15 is an illustrative flow chart of the software for issuing commands in general to the security management system in accordance with the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Prior to discussing FIGS. 2-15 which detail the security management system in accordance with the present invention, a general background summary of the operation of the personal computer protected by the security management system of the present
invention merits review.
Referring now to FIG. 1, a computer system S according to the present invention is shown. In the preferred embodiment, there are two primary buses located in the system S. The first bus is the PCI or Peripheral Component Interconnect bus P which
includes an address/data portion and control signal portion. The second primary bus in the system S is the ISA bus I. The ISA bus I includes an address portion, a data portion 110, and a control signal portion 112. The PCI and ISA buses P and I form
the backbones of the system S.
A CPU/memory subsystem 100 is connected to the PCI bus P. The processor 200 is preferably the Pentium processor from Intel, preferably operating externally at 50 or 60 MHz, but could be an 80486 from Intel or processors compatible with the 80486
or Pentium or other processors if desired. The processor 200 provides data, address, and control portions 202, 204, 206 to form a host bus HB. A level 2 (L2) or external cache memory system 208 is connected to the host bus HB to provide additional
caching capabilities to improve performance of the computer system. The L2 cache 208 may be permanently installed or may be removable if desired. A cache and memory controller and PCI bridge chip 210, such as the 82434X chip from Intel Corporation or
the chip described in patent applications Ser. Nos. 08/324,016, entitled "SINGLE BANK, MULTIPLE WAY CACHE MEMORY" pending and 08/324,246, entitled "SYSTEM HAVING A PLURALITY OF POSTING QUEUES ASSOCIATED WITH DIFFERENT TYPES OF WRITE OPERATIONS FOR
SELECTIVELY CHECKING ONE QUEUE BASED UPON TYPE OR READ OPERATION", filed Oct. 14, 1994, now U.S. Pat. No. 5,634,073, and hereby incorporated by reference, is connected to the control portion 206 and to the address portion 204. The bridge chip 210 is
connected to the L2 cache 208 as it incorporates the cache controller and therefore controls the operation of the cache memory devices in the L2 cache 208. The bridge chip 210 is also connected to control a series of data buffers 212. The data buffers
212 are preferably similar to the 82433LX from Intel, or those described in patent applications Ser. Nos. 08/324,246 now U.S. Pat. 5,634,073 as incorporated above and 08/323,263 entitled "DATA ERROR DETECTION AND CORRECTION SYSTEM", filed Oct. 14,
1994, now U.S. Pat. No. 5,555,250 and hereby incorporated by reference, and are utilized to handle memory data to a main memory array 214. The data buffers 212 are connected to the processor data portion 202 and receive control signals from the bridge
chip 210. The data buffers 212 are also connected to the PCI bus P for data transfer over that bus. The data buffers 212 provide a memory data bus 218 to the memory array 214, while a memory address and memory control signal bus 220 is provided from
the bridge chip 210.
A video controller 300 is connected to the PCI bus P. Video memory 304 is used to store the graphics data and is connected to the video graphics controller 300 and a digital/analog converter (RAMDAC) 306. The video graphics controller 300
controls the operation of the video memory 304, allowing data to be written and retrieved as required. A video connector 308 is connected to the RAMDAC 306. A monitor (not shown) is connected to the video connector 308.
A network interface controller (NIC) 120 is connected to the PCI bus P. Preferably the controller 120 is a single integrated circuit and includes the capabilities necessary to act as a PCI bus master and slave and the circuitry to act as an
Ethernet interface. Alternate Ethernet connectors 124 are provided on the system S and are connected to filter and transformer circuitry 126, which in turn is connected to the controller 120. This forms a network or Ethernet connection for connecting
the computer system S to a local area network (LAN).
A PCI-ISA bridge 130 is provided to convert signals between the PCI bus P and the ISA bus I. The PCI-ISA bridge 130 includes the necessary address and data buffers and latches, arbitration and bus master control logic for the PCI bus, ISA
arbitration circuitry, an ISA bus controller as conventionally used in ISA systems, an IDE (integrated drive electronics) interface, and a DMA controller. Preferably the PCI-ISA bridge 130 is a single integrated circuit, but other combinations are
possible. A series of ISA slots 134 are connected to the ISA bus I to receive ISA adapter cards. A series of IDE slots 133 are connected to the ISA bus I and the PCI-ISA bridge chip 130 to receive various IDE devices, such as hard disk drives, tape
drives and CD-ROM drives. A series of PCI slots 135 are connected to the PCI bus P to receive PCI adapter cards.
A combination I/O chip 136 is connected to the ISA bus I. The combination I/O chip 136 preferably includes a floppy disk controller, real time clock (RTC), CMOS memory, two UARTs, various address decode logic and security logic to control access
to the CMOS memory and the power on password values. A floppy disk connector 138 for receiving a cable to a floppy disk drive is connected to the combination I/O chip 136 and the ISA bus I. Serial port connectors 137 are also connected to the
combination I/O chip 136. A buffer 144 is connected to the ISA bus I to provide an additional X bus X for various additional components of the computer system. A flash ROM 154 receives its control, address and data signals from the X bus X. Preferably
the flash ROM 154 contains the BIOS information for the computer system and can be reprogrammed to allow for revisions of the BIOS. An 8042 or keyboard controller 156 is connected to the X bus X and ISA bus I address and control portion. The keyboard
controller 156 is of conventional design and is connected in turn to a keyboard connector 158 and a mouse or pointing device connector 160.
A miscellaneous system logic chip 132 is connected to the X bus X. The miscellaneous system logic chip 132 contains counters and timers as conventionally present in personal computer systems, an interrupt controller for both the PCI and ISA buses
P and I, enhanced parallel port circuitry and power management logic, as well as other miscellaneous circuitry. Additionally, the miscellaneous system logic chip 132 includes circuitry of a security management system according to the present invention
and so is connected to the flash ROM 154 through write protection logic 540.
This is an exemplary computer system S and other variations could readily be developed by one skilled in the art.
Turning to FIG. 2, the operation of the security device is provided in greater detail as a flowchart. The preferred embodiment of the security device comprises the following elements: a command register and decoder for the security device; a
data/status register for communicating with the computer, an eight byte register file to store password for each of the protected resources, and password verification logic.
Commands are preferably issued from the computer to the security device at a predetermined address. Status may be read from the last resource, or slot, indexed. The security device is capable of protecting a plurality of resources or slots. In
the preferred embodiment shown in detail, only a single resource is protected, but at various locations reference is explicitly made to the plurality of resources or slots and those skilled in the art can readily determine appropriate modifications where
not specifically discussed. A Read Status command is configured so that the status register of any particular resource, or slot, can be read, without affecting other operations occurring to a resource or slot, such as unlocking or changing a password.
Access to a specific resource, or slot, in the security device is performed with an indexed address scheme. Two addresses are used for the indexing scheme, one address is for commands, while the second address is the data/status register. The second
address acts as a data register for a write cycle and as a status register during a read cycle. The index is placed in the upper three bits of the command register.
The format of the command register of the preferred embodiment is as follows:
______________________________________ Read or Bit(s) Write Name Description ______________________________________ 7-5 R/W IDX[2:0] Slot index which point to a particular resource, or slot 4 R/W Reserved Reserved bit 3-0 R/W CMD[3:0]
Command bits executed by security device ______________________________________
The slot index, or resource index, encoding for the preferred embodiment is as follows:
______________________________________ Slot Index Encoding Index Bits Slot IDX2 IDX1 IDX0 Number ______________________________________ 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7
______________________________________
As can be seen, the preferred embodiment allows up to eight slots, or resources, to be controlled by the security device. Bits 0-3 of the preferred embodiment contain the command sent to the security device which is encoded as follows:
______________________________________ Commands Black Box Command Command Code Command Description ______________________________________ Read Status X0H Changes index pointer to the slots so that a status read can occur from another slot.
Store a X1H Receives the next eight bytes written to the Password data/status port and updates as the new pass- word. Protect X2H Enables guarding by the security device after Resources storing a password or after access to a se- cured resource is
completed. Access X4H Once this command is given, the next eight Resources bytes written to the data/status port are com- pared against the stored password. If the com- pare is good, the security device will unlock the resource and allow changes. A
Protect Re- sources command must be given when done making changes so that the resource is once again protected. Permanently X8H Permantently lock all resources. Future Lock accesses to protected system resources Resources are not possible unless
power is cycled. A status register read is possible. ______________________________________
In addition to sending commands to the security device, status can be read from the security device at any time, by reading the status/data register, preferably located at a second predetermined address adjacent to the first predetermined
address. The data/status register serves two purposes. When serving as the data register, the register is used when storing passwords or verifying passwords (accessing resources).
To store passwords, the Store Password command must first be sent to the security device. Then, the next eight writes to the data/status register cause the data written to the data/status register to be stored as the password for the security
device. Eight bytes are preferably written to the data/status register in the preferred embodiment, although the actual size of the data/status register may be smaller or greater. If another command for the security device arrives before all eight
bytes have been stored for the password, the password storage operation for that slot in the security device aborts and the password then contains undefined data.
The status register provides status information on a particular resource when read. The status register is defined below.
______________________________________ Commands READ OR BITS WRITE NAME DESCRIPTION ______________________________________ 7-5 R IDX[2:0] Slot index bits 4-3 R Reserved Reserved bits 2 R PL Permanently Locked 1 R D Delay in progress if set
due to mis- match 0 R U UNLOCK.sub.-- Pin state ______________________________________
Bits 7-5 provide an indication of which particular resource or slot the remaining bits identify. The PL bit indicates when set that this resource is permanently locked. The D bit indicates when set that a one second delay is in progress due to
a password mismatch. The U bit is the state of the UNLOCK.sub.-- pin or signal for the resource.
For overview purposes, the simplified operation of the security device after initialization is next discussed. To verify a password, first an Access Resources command must be sent to the security device. Then, the next eight writes to the
data/status register cause the byte written to the data/status register to be compared against a byte of the password stored in the security device. If correct password is provided, the resource is unlocked, otherwise the security device is unavailable
for one second before the next command can be sent.
Turning to FIG. 2, the general process of unlocking a slot after initialization is shown. In step 402 a determination is made if an Access Resources command is received by the security device. Until an Access Resource command is received, the
operation essentially loops at step 402. The resources have to have been protected by the Protect Resources command during initialization as described below in order for the Access Resources command to be recognized. Then in step 404, a determination
is made if a permanent lock resources (PLR) bit has been set to check the condition that a permanently lock resources command has been issued. If so, the Access Resources command is ignored. Once the Access Resources command has been received and the
resource or slot is not permanently locked, the security device receive a byte representative of a key or password written to the data/status port at step 406. The byte is compared against the appropriate byte in the password stored in the register file
in the security device at step 408. Bytes written to the data/status register are received in the same order as received in the Store Password command. After a byte is received, a compare between the received key byte and the corresponding byte in the
password register file is performed. If the key byte fails to match the password byte, a MISMATCH bit is set at step 410. The comparison sequence is repeated at step 412 until the last byte, or the eighth byte in the preferred embodiment, has been
checked. The status register is not updated until all eight bytes have been received.
In the preferred embodiment, eight compares must occur before the result of the verification is checked. If a command is written to the command register when the security device is expecting to receive bytes to compare against the stored
password, the password verification phase is aborted and the command that was received by the security device is ignored.
In step 414 after the last byte has been received, if the mismatch flag is set, control proceeds to step 416 where the unlock output is kept inactive and a one-second delay occurs before another attempt to access the security device can occur.
Once the Access Resources command has been validated, the security unit responds to the commands given to it. Further, the security unit asserts the UNLOCK.sub.-- bit signal low or active in step 418. The UNLOCK.sub.-- signal is used to signal
that the access to the secured resources has been granted and is used to enable the secured resources.
If the command is a Read Status command in step 420, then in step 422 the security unit enables the status register of the indexed slot to return the status of that slot back to the computer.
In step 424, if the command is a Store Password command, the next eight bytes written to the data/status port are to be stored as the new password and this is done in step 426.
In step 428, if the command is a Protect Resources command, the security feature is restarted such that a new password verification is required. The UNLOCK.sub.-- output is deasserted or set high after receiving this command in step 430. Once
this command is given, the only way to change security device protected resources is to reissue an Access Resources command and reprovide the password. In step 432, if the user issues a Permanently Lock resources command, the PLR bit is set in step 434. If this command is written to the security device, the resources are permanently locked. Security device access to protected system resources is no longer possible unless power is cycled. However, a status register read is still possible.
For simplicity, while this description focuses on protecting only one resource, it is within the scope of the invention to have multiple resources located in multiple slots for passwords in the security device. This is done by the use of the
different index values, each referencing a different resource or slot. In this description, the index value is always assumed to be zero to access the first slot. Thus, in a multiple resource embodiment, there are a plurality of eight byte password
registers used to store passwords. In the multiple resource embodiment, the security device has an UNLOCK_ output for each slot. The additional slots in the security device can include slots for power-on password, administrator password, Safe Start
hash codes, among others. The power-on password slot controls the power-on password, which is currently only changeable at boot time. If a slot is provided then the power-on password can be changed at run-time. In addition to the power-on password
slot, another slot may be used to address the rest of the protected areas that are accessible through the Administrator password. Further, Safe Start codes resource is another candidate.
The Safe Start hash codes are used to verify the integrity of computer data for effects of computer viruses. The Safe Start system provides verification independent of and transparent to the operating system because it uses a reserved non-DOS
hard disk partition system to check on the DOS partition of the computer. This system is disclosed in U.S. patent application Ser. No. 08/315,702 entitled "TRANSPARENT, SECURE COMPUTER VIRUS DETECTION METHOD AND APPARATUS" now U.S. Pat. No.
5,537,540 and in U.S. application Ser. No. 08/231,443 entitled "METHOD AND APPARATUS FOR ASSESSING INTEGRITY OF COMPUTER SOFTWARE", now U.S. Pat. No. 5,421,006 both of which are hereby incorporated by reference. The Safe Start hash codes could also
be protected by a slot in the security device. Since these hash codes are never visible to the user, this section may permanently locked by the security device.
Turning to FIG. 3, a state machine 438 controlling the security device according to the invention is disclosed. The states of the machine are sequenced on the falling edge of a write instruction to the command register. As shown in FIG. 4, the
state machine has an IDLE state 440, an ACC.sub.-- RESOURCE state 442 in which access to a secured resource may be granted, a STORE.sub.-- PASSWD state 444 in which a new password can be stored, and a DELAY state 446 for delaying responses for a period
of time, preferably one second, if the key provided does not match the password.
Upon reset, the state machine 438 is in IDLE state 440. In this state, only commands are accepted. The IDLE state 440 transitions to the ACC.sub.-- RESOURCE state 442 when a command is written to the command register (WRITE.sub.-- COM), this
command is an access resource request (ACC.sub.-- RES.sub.-- CMD), the locked or unlocked status signal (UNLOCK.sub.--) is deasserted or high and the lock status signal (PLOCK.sub.-- STAT) is not asserted. The PLOCK.sub.-- STAT signal, if not asserted,
indicates that the Permanent Resources command has not been issued. Once in the ACC.sub.-- RESOURCE state 442, the state machine 438 may transition back to the IDLE state 440 or to the DELAY state 446.
The transition from the ACC.sub.-- RESOURCE state 442 to the IDLE state 440 occurs when dat | | |
