An apparatus comprising a plurality of storage devices and a scheduler circuit. Each of the plurality of storage devices may be configured to store and present one or more packets of a data stream over one or more first busses operating at a first speed. The scheduler circuit may be configured to determine which of the plurality of storage devices transmits the packets of the data stream. A second bus that may be configured to carry look ahead information and synchronize the plurality of devices. The second bus may operate at a second speed.

Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port coupled to a channel data bus that serves the plurality of channel interfaces. The buffer circuit further includes an arbitrator (24) for arbitrating access to the dual port memory by individual ones of the channel interfaces over the channel data bus; an address generator (26) for generating dual port memory addresses for reading and writing data using the CPU data bus and the channel data bus; and a control unit (20) and allocator (22) that are programmable by the CPU for specifying individual ones of buffer locations and sizes within the dual port memory for individual ones of the channel interfaces, and for enabling and disabling individual ones of the buffers.

A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.