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Claims  |
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We claim:
1. A semiconductor memory device comprising:
an array of memory cells operable to store data therein;
a plurality of output terminals;
a control circuit coupled to the array of memory cells and being operable
to transfer data from at least one memory cell to one of the output
terminals during a read operation;
a test circuit coupled to the array of memory cells, the test circuit, in
response to a test mode signal, testing data written to at least one
memory cell of the array during the read operation and outputting a test
signal based on the testing to one of the output terminals; and
a data path coupling at least one of the memory cells being tested by the
test circuit to one of the output terminals during the read operation.
2. The semiconductor memory device of claim 1 wherein the array of memory
cells includes at least first and second sets of sub-arrays, each set
having eight sub-arrays corresponding to a data word; and
wherein the test circuit includes first and second compare circuits, the
first compare circuit comparing bits in a first data word written to the
first set of sub-arrays to each other and outputting a pass value for the
test signal if all of the bits in the first data word match, and
the second compare circuit comparing bits in a second data word written to
the second set of sub-arrays to each other and to at least one bit from
the first data word and outputting a pass value for the test signal if all
of the bits of the second data word and the one bit from the first data
word match.
3. The semiconductor memory device of claim 1 wherein the array of memory
cells includes first and second sub-arrays, and wherein the test circuit
tests data written to the first sub-array by comparing data written to the
first sub-array to data written to the second sub-array during testing of
the semiconductor memory device, and wherein the test circuit outputs a
pass value for the test signal if the data written to the first sub-array
corresponds to the data written to the second sub-array.
4. The semiconductor memory device of claim 1, further comprising a latch
coupled between the test circuit and one of the output terminals, the
latch storing the test signal and allowing the test signal to be read from
the latch through the one output terminal.
5. The semiconductor memory device of claim 1, further comprising a data
output register having an input switch, a master latch and a slave latch,
and wherein the array of memory cells includes first and second
sub-arrays, the input switch being coupled to the first sub-array and
electrically disconnecting the data output register from the first
sub-array in response to the test mode signal;
the master latch being coupled to the passgate and selectively receiving
the test signal in response to the predetermined signal or the data stored
in the first sub-array in the absence of the predetermined signal, and
outputting the test signal or stored data in response thereto,
respectively; and
the slave latch being coupled between the master latch and at least one
output terminal, wherein the slave latch provides the test signal or the
stored data to the one output terminal.
6. The semiconductor memory device of claim 1 wherein the plurality of
output terminals includes first and second output terminals, wherein a
test circuit is coupled to the first output terminal to provide the test
signal thereto, and wherein the second output terminal is coupled to the
data path, and wherein the semiconductor memory device further comprises
an additional output terminal and a passgate coupled between the test
circuit and the additional output terminal, the passgate providing the
test signal to the additional output terminal in response to the test mode
signal.
7. The semiconductor memory device of claim 1, further comprising a 2:1
multiplexing circuit coupled between the test circuit and one of the
output terminals, wherein the test circuit includes at least one exclusive
OR gate, and the wherein the array of memory cells are synchronous dynamic
random access memory cells.
8. The semiconductor memory device of claim 1, further comprising a switch
coupled between the test circuit and one of the output terminals to
selectively permit the test circuit to provide the test signal to the one
output terminal.
9. The semiconductor memory device of claim 1 wherein the plurality of
output terminals includes first and second terminals, the first terminal
being coupled to the test circuit to allow the test circuit to output the
test signal thereto, and the second terminal being coupled to the data
path.
10. The semiconductor memory device of claim 1, further comprising a switch
coupled to the test circuit, data path, and a single output terminal, the
switch selectively coupling the test circuit and the data path to the
single output terminal.
11. A circuit device comprising:
a plurality of circuit cells operable to store data therein, the plurality
of circuit cells including first and second sub-arrays of circuit cells;
a plurality of output terminals, including first and second output
terminals coupled to the first and second sub-arrays, respectively;
a control circuit coupled to the first and second sub-arrays and being
operable to transfer data from the first and second sub-arrays to the
first and second output terminals, respectively;
a test circuit coupled to the control circuit and the first and second
sub-arrays, the test circuit, in response to a predetermined signal,
testing data written to the first sub-array and outputting a test signal
based on the testing; and
a switch coupled to the test circuit and one of the plurality of output
terminals, the switch receiving the predetermined signal from the control
circuit and coupling the test circuit to the one output terminal in
response thereto.
12. The circuit device of claim 11 wherein the plurality of circuit cells
includes at least first and second sets of sub-arrays, each set having
eight sub-arrays corresponding to a data word; and
wherein the test circuit includes first and second compare circuits, the
first compare circuit comparing bits in a first data word written to the
first set of sub-arrays to each other and outputting a pass value for the
test signal if all of the bits in the first data word match, and
the second compare circuit comparing bits in a second data word written to
the second set of sub-arrays to each other and to at least one bit from
the first data word and outputting a pass value for the test signal if all
of the bits of the second data word and the one bit from the first data
word match.
13. The circuit device of claim 11 wherein the test circuit tests data
written to the first sub-array by comparing data written to the first
sub-array to data written to the second sub-array during testing of the
circuit device, and wherein the test circuit outputs a pass value for the
test signal if the data written to the first sub-array corresponds to the
data written to the second sub-array.
14. The circuit device of claim 11, further comprising a latch coupled
between the test circuit and the first output terminal, the latch storing
the test signal and allowing the test signal to be read from the latch
through the first output terminal.
15. The circuit device of claim 11, further comprising a data output
register having an input switch, a master latch and a slave latch, the
input switch being coupled to the first sub-array and electrically
disconnecting the data output register from the first sub-array in
response to the predetermined signal;
the master latch being coupled to the passgate and selectively receiving
the test signal in response to the predetermined signal or the data stored
in the first sub-array in the absence of the predetermined signal, and
outputting the test signal or stored data in response thereto,
respectively; and
the slave latch being coupled between the master latch and the first output
terminal, wherein the slave latch provides the test signal or the stored
data to the first output terminal.
16. The circuit device of claim 11, further comprising an additional output
terminal and a passgate coupled between the test circuit and the
additional output terminal, the passgate providing the test signal to the
additional output terminal in response to the predetermined signal.
17. The circuit device of claim 11 wherein the switch is a 2:1 multiplexing
circuit, the test circuit includes at least one exclusive OR gate, and the
wherein the plurality of circuit cells are synchronous dynamic random
access circuit cells.
18. A semiconductor memory device comprising:
a plurality of memory cells operable to store data therein, the plurality
of memory cells including first and second sets of sub-arrays of memory
cells, each set having eight sub-arrays corresponding to a data word;
a control circuit coupled to the plurality of memory cells and being
operable to write data to, and read data from, the plurality of memory
cells; and
a test circuit having first and second compare circuits, the first compare
circuit comparing bits in a first data word written to the first set of
sub-arrays to each other and outputting a pass value for a test signal if
all of the bits in the first data word match, and the second compare
circuit comparing bits in a second data word written to the second set of
sub-arrays to each other and to at least one bit from the first data word
and outputting a pass value for the test signal if all of the bits of the
second data word and the one bit from the first data word match.
19. A computer system comprising:
an input device;
an output device;
an address bus;
a data bus;
a set of control lines;
a memory controller coupled to the address and data buses and to the set of
control lines;
a processor coupled to the input and output devices, to the address and
data buses and to the set of control lines; and
a memory device coupled to the memory controller through the address and
data buses and the set of control lines, the memory device comprising:
an array of memory cells operable to store data therein;
a plurality of output terminals;
a control circuit coupled to the array of memory cells and being operable
to transfer data from at least one memory cell to one of the output
terminals during a read operation;
a test circuit coupled to the control circuit and array of memory cells,
the test circuit, in response to a test mode signal, testing data written
to at least one memory cell of the array during the read operation and
outputting a test signal based on the testing to one of the output
terminals; and
a data path coupling at least one of the memory cells being tested by the
test circuit to one of the output terminals during the read operation.
20. The computer system of claim 19, further comprising a latch coupled
between the test circuit and the one output terminal, the latch storing
the test signal and allowing the test signal to be read from the latch
through the one output terminal.
21. The computer system of claim 19, further comprising:
a data output register having an input switch, a master latch and a slave
latch, wherein the array of memory cells includes first and second
sub-arrays, the input switch being coupled to the first sub-array and
electrically disconnecting the data output register from the first
sub-array in response to the test mode signal;
the master latch being coupled to the passgate and selectively receiving
the test signal in response to the test mode signal or the data stored in
the first sub-array in the absence of the test mode signal, and outputting
the test signal or stored data in response thereto, respectively; and
the slave latch being coupled to the master latch and the one output
terminal, wherein the slave latch provides the test signal or the stored
data to the first output terminal.
22. A semiconductor device testing apparatus comprising:
a die having a semiconductor circuit formed thereon, the semiconductor
circuit having a plurality of memory cells operable to store data therein;
a plurality of electrically conductive leads coupled to the semiconductor
circuit on the die, the leads including address leads for receiving
address signals, and wherein the plurality of memory cells are addressable
by electrically conductive row and column lines based on an address word
applied to the address leads;
a control circuit coupled to the memory cells and being operable to
transfer data from the memory cells to one of the first and second leads;
a test circuit coupled to the control circuit and the memory cells, the
test circuit testing data written to at least one memory cell and
outputting a test signal based on the testing to one of the leads;
a data path coupling at least one of the memory cells being tested by the
test circuit to one of the leads during the read operation;
an encapsulating material that encapsulates the die and at least a portion
of the plurality of leads to form a packaged chip;
testing circuitry for applying the address signals; and
a socket for releasably holding the packaged chip and electrically coupling
the plurality of leads with the testing circuitry.
23. The semiconductor device testing apparatus of claim 22, further
comprising a pick and place apparatus for automatically inserting the
packaged chip into the socket.
24. A method of testing a semiconductor memory device having an array of
memory cells and at least one output terminal, the method comprising the
steps of:
entering into a test mode;
writing data to at least one memory cell of the array;
testing the data written to the memory cell;
providing a test signal indicating the results of the testing;
selectively providing the test signal to one of the output terminals when
the memory device is in the test mode; and
reading the data from the memory cell and providing the data to one of the
output terminals.
25. The method of claim 24, further comprising the steps of:
reading the data from one output terminal; and
reading the test signal from the one output terminal at a time after the
step of reading the data from the one output terminal.
26. The method of claim 24 wherein the memory device includes first and
second sub-arrays of memory cells, and includes first and second output
terminals respectively coupled thereto, wherein the step of selectively
providing the test signal provides the test signal to the first output
terminal, and wherein the step of reading the data provides the data to
the second output terminal.
27. The method of claim 24, further comprising the steps of:
reading the data from a first output terminal; and
reading the test signal from a second output terminal at a time after the
step of reading the data from the first output terminal.
28. A method of testing a semiconductor memory device having first and
second sets of memory cells, the method comprising the steps of:
writing first and second sets of data to the first and second sets of
memory cells;
reading the first set of data from the first set of memory cells and
comparing the first set of data with itself;
reading the second set of data from the second set of memory cells and
comparing the second set of data to itself and to at least one bit from
the first set of data; and
generating a test signal based on the reading steps. |
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Claims |
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Description |
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TECHNICAL FIELD
This invention relates generally to computers, and more particularly to
memory devices and methods of testing such devices.
BACKGROUND OF THE INVENTION
Computer designers desire fast and reliable memory devices that will allow
them to design fast and reliable computers. Manufacturers of memory
devices, such as random access semiconductor memories, must test a full
range of functionality and timing characteristics of the memory devices in
order to provide a reliable product to their customers. Because each
memory cell of the device must be tested, the time and equipment necessary
for testing memory devices having increasing density represents a
significant portion of the overall manufacturing cost of such devices. Any
reduction in the time to test each unit will reduce manufacturing costs.
Semiconductor manufacturers have developed fast testing routines to allow a
greater number of chips to be tested simultaneously using a given testing
device. One known testing routine, Jedec, simply compares the data written
to a memory device with the data read from that memory device, and assigns
a 1 value to one or more memory cell addresses if the data matches
(passes), or a 0 if the data does not match (fails). While the Jedec
routine is fast, it does not output the actual data written to the memory
device. As a result, if the tester outputs a continuous string of 1s,
indicating that the memory device passes, a technician is unsure whether
the device actually passes, or if an error has occurred in the device, or
at some point along the path from the device to the tester, to cause such
an output.
To compensate for this shortcoming of the Jedec routine, a Micron Test Mode
Routine provides three outputs. The Micron Routine outputs the actual
data, as a 0 or a 1, and a mid-level tri-state value therebetween. If the
tri-state value is output, rather than a 1 or a 0, the technician
recognizes that an error has occurred. Unfortunately, while the Micron
Routine provides superior testing of most semiconductor devices, the
routine typically cannot bias the output back to the tri-state value
before the beginning of the next read/write cycle rapidly enough to allow
current high-speed memory devices to be tested at their normal operating
speed. As a result, such high-speed memory devices must be tested at
speeds slower than their typical operating speed.
To save testing time and cost, manufacturers of memory devices increasingly
automate the testing procedure so that a tester applies the testing
routine simultaneously to several chips. Automated testing is most easily
accomplished after the memory device has been packaged as a semiconductor
chip, because the chip can be automatically inserted into a test socket
using pick and place machinery. Automated testing circuitry then performs
the testing routine by applying predetermined voltages and signals to the
chip, writing test data patterns to the memory, reading data, and
analyzing the results to detect memory speed, timing, failures, etc. The
more chips that can be tested simultaneously, the greater testing time
savings per chip.
Most testers used in testing semiconductor chips are expensive. For
example, a current tester manufactured by Teradyne has 128 input/output
("I/O") lines. To maximize the number of chips that this tester can test
simultaneously, the on-chip data input/output lines, or "DQ lines," are
multiplexed so that fewer I/O lines from the tester are required to be
coupled to each chip. For example, the tester writes a predetermined data
pattern simultaneously to multiple locations in each memory device and
then accesses the written data during a read cycle. Comparator circuits
fabricated on-chip compare the data read from the multiple locations and
indicate whether all the data read matches the data written. If the chip
has 32 DQ lines (DQ0-DQ31), on-chip 4:1 multiplexers and testing circuitry
compress data onto only 8 of the 32 DQ lines. As a result, only 8 of the
128 lines of the tester are required for each chip. Consequently, the
tester's 128 I/O lines can simultaneously test 16 chips.
In another solution, certain semiconductor memory devices, manufactured by
Micron Technology, Inc., provide on-chip test mode circuitry that helps
compensate for such delays during testing of devices. Under such test mode
circuitry, the external testing device writes data to the chip during a
first interval, and then writes the same data again to the DQ lines during
a second interval. During the second interval, while the data is written
again to the DQ lines, the data previously written to the memory device is
read therefrom and latched. On-chip comparators then compare the latched
data to the data written during the second interval. If the latched data
equals the data written during the second interval, then the chip passes.
Such a device can rapidly analyze the read data written to the device.
While the above solutions can detect for typical cell-to-cell defects and
functionality of the chip, they cannot accurately test the speed of the
chips. As semiconductor memory chips provide increasingly faster data I/O
rates, particularly with synchronous DRAMs, data is required to be
transferred to and from the chips in as little as 9 nanoseconds or less,
based on a 10-nanosecond or faster clock cycle. As a result, such chips
provide only a 1-nanosecond margin of error. Today's increasingly fast
memory devices require highly precise generation of timing signals and
precise measurement of the memory device's response thereto. Gate delays
caused by the multiplexing circuitry required during testing cause the
data to be read from the chips in greater than 10 nanoseconds. As a
result, the tester cannot determine if the chip accurately output data
within the required 9 nanoseconds. In other words, the on-chip testing
circuitry prohibits the tester from testing the speed of such chips.
Obviously, it is desirable to determine the performance, and thus the speed
of, semiconductor memory chips, especially high-speed chips. Additionally,
because of manufacturing process tolerance and variations, one memory
device of a particular design may be faster than another memory device of
the very same design. Manufacturers therefore typically also desire to
test the speed of such chips so that such chips can be sorted based on
speed grades. To provide such speed testing, typical address compression
mode testing, and on-chip multiplexing of DQ lines, must be abandoned. As
a result, where 16 or more chips could previously be simultaneously tested
using multiplexing, only 4 of such chips can be simultaneously speed
tested because all 32 DQ lines of each chip must be coupled to the
tester's I/O lines. As a result, there is a need to simultaneously speed
test an increasing number of chips using a given tester.
One solution has been to purchase a larger number of testers, or more
expensive testers having a greater number of I/O lines. However, as noted
above, such testers are quite expensive.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device that can be
efficiently speed tested, and which overcomes at least the shortcomings of
the prior art discussed above. The memory device requires, at a minimum,
only two I/O lines from an external testing device to be coupled thereto.
A first DQ line from the memory device provides a direct data path from
the array so that the external tester can read data from the array at the
maximum speed of the memory device. Test mode circuitry for multiplexing
and comparing multiple DQ lines in address compression mode is coupled to
two or more DQ lines, including the first DQ line. The compression mode
testing circuitry can include on-chip comparators that compare the data
simultaneously written to, and read from, the memory device. The
comparison circuitry outputs a data test flag indicating whether the data
read from the memory device matches or whether the data does not match.
The test flag is output through a multiplexer to a second DQ line. As a
result, the speed of the device can be tested from the first DQ line,
while the results of on-chip comparison can be sampled at the second DQ
line. Importantly, the external testing device need not read the data from
the first DQ line simultaneously with the test data flags from a second DQ
line.
The present invention also embodies a method of reducing the number of
compare circuits required in on-chip test circuitry. To reduce the number
of exclusive OR gates, and thereby realize increased surface area on the
die, compare circuits compare not only bits of a given data word, but also
at least one bit from another data word. Therefore, rather than employing
two compare circuits that compare first and second data words, and a third
compare circuit that compares the results of the first two compare
circuits, the present invention avoids the need for the third compare
circuit by comparing the first data word in a first compare circuit with
at least one bit from the second data word.
In a broad sense, the present invention embodies a semiconductor memory
device having a plurality of memory cells, at least first and second
output terminals, a control circuit, a test circuit and a data path or
switch. The plurality of memory cells are operable to store data therein,
and include first and second sub-arrays of memory cells. The first and
second output terminals are coupled to the first and second sub-arrays,
respectively. The control circuit is coupled to the first and second
sub-arrays and is operable to transfer data from the first and second
sub-arrays to the first and second output terminals, respectively.
The test circuit is coupled to the control circuit and to the first and
second sub-arrays. The test circuit, in response to a test mode signal
from the control circuit, tests data written to the first sub-array and
outputs a test signal based on the testing. The switch receives the test
mode signal from the control circuit and couples the test circuit to the
first output terminal in response thereto. As a result, the test signal
can be provided to the first output terminal, while data stored in the
second sub-array can be provided to the second output terminal during the
testing.
Additionally, the present invention embodies a method of testing a
semiconductor memory device having at least first and second sub-arrays of
memory cells. The method includes the steps of: (a) entering into a test
mode; (b) writing data to the first and second sub-arrays; (c) testing the
data written to the first sub-array; (d) providing a test signal
indicating the results of the testing; (e) selectively providing the test
signal to an output terminal when the memory device is in the test mode;
and (f) reading the data from the second sub-array and providing the data
to a second output terminal.
Moreover, the present invention embodies a semiconductor memory device
having a plurality of memory cells, a control circuit and a test circuit.
The plurality of memory cells include first and second sets of sub-arrays
of memory cells, each set having eight sub-arrays corresponding to a data
word. The control circuit is coupled to the plurality of memory cells and
is operable to write data to, and read data from, the plurality of memory
cells.
The test circuit has first and second compare circuits. The first compare
circuit compares bits in a first data word written to the first set of
sub-arrays to each other and outputs a pass value for a test signal if all
of the bits in the first data word match. The second compare circuit
compares bits in a second data word written to the second set of
sub-arrays to each other and to at least one bit from the first data word,
and outputs a pass value for the test signal if all of the bits of the
second data word and the one bit from the first data word match.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a memory device having a test mode
circuit according to the present invention.
FIG. 2 is a block diagram showing details of the test mode circuit and
associated circuitry of the memory device of FIG. 1.
FIG. 3 is schematic diagram of the test mode circuit and related circuitry
of the memory device of FIG. 1.
FIG. 4 is a block diagram of an alternative embodiment of the test mode
circuit of the memory device of FIG. 1.
FIG. 5 is a part isometric view, part block diagram of a testing station
for testing a chip containing the memory device of FIG. 1.
FIG. 6 is a block diagram of a computer system containing the memory device
of FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a block diagram of the preferred embodiment of a memory device
10 according to the present invention. The memory device 10 is a
synchronous dynamic random access memory (SDRAM) device that includes as
its central memory element left and right memory array banks 11A and 11B.
Each of the memory arrays 11A and 11B includes a plurality of memory cells
(not shown) arranged in rows and columns. A control logic circuit 12
controls the data transfer steps associated with a read or write access to
the memory cells in the arrays 11A and 11B. In one embodiment, each of the
arrays 11A and 11B has memory cells arranged in 512 rows by 256 columns by
32 bits. The memory device 10 has a width of 32 bits--meaning that each
memory address (combined bank, row and column address) corresponds to a
respective 32-bit memory cell in one of the arrays 11A and 11B, and a
processor (not shown in FIG. 1) operates on data elements of 32 bits each.
A system clock (not shown) provides a CLK signal to the control circuit 12
of the memory device 10. Command signals are provided to the control
circuit 12 and decoded by command decode circuitry 14. These signals are
well known in the art, and include signals such as CKE (clock enable), CS
(chip select), WE (write enable), RAS (row address strobe) and CAS (column
address strobe). Distinct combinations of the various command signals
constitute distinct processor commands. For example, the combination of CS
low, WE high, RAS low and CAS high can represent an ACTIVE command.
Examples of other well-known commands include READ, WRITE, NOP and
PRECHARGE. Although the processor actually produces distinct command
signals that in combination are registered and decoded as commands by the
memory device 10, it is convenient to refer to these commands as being
issued by the processor.
The control circuit 12 sends control signals on control lines (not shown)
to other parts of the memory device 10, corresponding to the
processor-issued command. These control signals control the timing of
access to the memory cells in arrays 11A and 11B. The memory device 10 is
also provided with an address of the memory location to be accessed on a
10-bit wide address bus 15, including a bank address specified by address
bit BA and a row or column address specified by address bits A0-A8. The
address is input to an address register 16 which provides the address
information to the control circuit 12, a row-address mux 17, and a
column-address latch and decode circuit 20.
In response to one or more control signals provided by the control circuit
12, the row-address mux 17 multiplexes row address information and
provides it to one of two row-address latch and decode circuits 18A and
18B corresponding to the memory banks 11A and 11B to be accessed. In
response to one or more control signals provided by the control circuit
12, each of the row latch and decode circuits 18A and 18B takes a row
address provided by the row-address mux 17 and activates a selected row of
memory cells (not shown) in the memory array 11A and 11B by selecting one
of several row access lines 22A and 22B, respectively. In response to one
or more control signals provided by the control circuit 12, the column
latch and decode circuit 20 takes a column address provided by the address
register 16 and selects one of several column access lines 24A and 24B,
each of which is coupled to one of the memory arrays 11A and 11B by one of
two I/O interface circuits 26A and 26B, respectively. In response to one
or more control signals provided by the control circuit 12, each of the
I/O interface circuits 26A and 26B selects the 32 memory cells
corresponding to the column location in an activated row.
The I/O interface circuits 26A and 26B include sense amplifiers which
determine and amplify the logic state of the selected memory cells. The
I/O interface circuits 26A and 26B also include I/O circuits that gate
data to 32 data output registers 28 and from a data input register 30,
responsive to one or more control signals provided by the control circuit
12. The data registers 28 and 30 are connected to a 32-bit wide data bus
31 at DQ pads DQ0-DQ31 to transfer output data Q0-Q31 to a processor and
input data D0-D31 from a processor, responsive to one or more control
signals provided by the control circuit 12.
The memory device 10 includes a refresh control circuit 32 which,
responsive to one or more control signals provided by the control circuit
12, initiates regular and periodic activation of each of the rows of the
memory cells in the arrays 11A and 11B for purposes of data refresh, as is
well known in the art. In response to one or more control signals provided
by the control circuit 12, a respective one of the I/O interface circuits
A and B senses data stored in the memory cells of the refresh-activated
row and rewrites values corresponding to the stored data in each of the
memory cells.
The memory device 10 is preferably formed on a single semiconductor
substrate or die. Several output terminals or pads, electrically coupled
to the address lines A0-A9, DQ lines DQ0-DQ31, and other lines, can be
formed at the periphery of the die. The die is preferably encapsulated by
a protective material to form a packaged chip, and several electrically
conductive leads or pins, which are electrically coupled to the pads,
extend from the chip (not shown in FIG. 1).
The memory device 10 also includes a test mode circuit 36 coupled to an
internal data output bus 37 connecting the I/O interface circuits 26A and
26B to the output register 28. The test mode circuit 36 is enabled by the
control circuit 12 when the control circuit has received instructions, in
the form of a special "address" of test key vector received by the control
circuit 12 and indicating that the memory device is to be operated in a
test mode. In particular, when the control circuit 12 is instructed to
operate the memory device 10 in the speed test mode, the control circuit
provides a test-enable signal TEST that enables the test mode circuit 36
to perform testing of the memory device. The test mode circuit 36 provides
a comparison signal or test data flag to the data output registers 28.
Referring to FIG. 2, the left array 11A is shown diagramatically as having
two sub-arrays, sub-array I and sub-array II. The sub-arrays I and II
receive incoming data, or outgoing data, through data paths 38 and 39,
respectively. The data paths 38 and 39, shown in the block diagram of FIG.
2, represent much of the circuitry coupled between the array 11A and the
data output registers 28, including the sense amplifiers, gating and I/O
circuits 26A. The data paths 38 and 39 are used during both normal and
test mode operation of the memory device 10, and therefore represent the
standard delays inherent between all of the DQ lines and the arrays.
For reasons of simplicity and clarity, only two sub-arrays for the array
11A, and two DQ lines, DQ5 and DQ7, are shown in FIG. 2. The memory device
10, however, has 32 sub-arrays and data paths corresponding to the 32 DQ
lines DQ0-DQ31. As explained more fully below, the 32 sub-arrays are
divided into four groups of 8 sub-arrays each, where each group outputs 1
bit to form an 8-bit word for each external address applied to the memory
arrays 11A and 11B. Therefore, for each external address, four data words
can be output. The test mode circuitry 36 compares bits of each word
together (e.g., compares the even bits together and the odd bits together
for each group of 8 sub-arrays), and outputs a test data flag to at least
one DQ line for each group (e.g., DQ line DQ6). At least one other DQ line
can then directly output the data to the same or an additional DQ pad to
allow both the test data flags on line DQ6 and direct data to be output by
the memory device 10.
As shown in FIG. 2, the test mode circuit 36 receives the outputs from the
data paths 38 and 39, compares the data from the sub-arrays I and II, and
outputs the test flag to a switch, such as 2:1 multiplexer 40. The
multiplexer 40 receives the TEST signal from the control circuit 12,
inverts the signal through an inverter 41 and provides both the inverted
and non-inverted test signal to a pair of cross-coupled passgates 42 and
43. The first passgate 42 receives the data from the data path 38, while
the second passgate 43 receives the test data flag from the test mode
circuit 36. If the incoming TEST signal has a high value, then the test
data flag from the test mode circuit 38 is passed by the passgate 43,
while if the TEST signal has a low value, the data from the data path 38
is output by the passgate 42. Output circuitry 44 receives the output from
the multiplexer 40, and is coupled at its output to the DQ pad DQ7. The
output circuitry 44 includes output amplifiers, one of the data output
registers 28, etc. The output circuitry 44 primarily includes standard
circuitry required to provide data to, and receive data from, the DQ pad
DQ7. Therefore, the output circuitry 44 contains standard delays inherent
in such circuitry, and which exist along all DQ lines in the memory device
10. Except as explained below, essentially the only delays along the DQ7
path, which differ from other DQ paths, are caused by the multiplexer 40
and test mode circuitry 36.
Output circuitry 45, substantially identical to output circuitry 44, is
coupled between the DQ pad DQ5 and the data path 39. Importantly, data
transferred to and from the sub-array II is transferred to and from
standard circuitry between the array and the DQ pad DQ5, i.e., the data
path 39 and the output circuitry 45. Therefore, an external testing device
can write data to, and read data from, the sub-array II and accurately
determine the speed of the memory device 10, since no additional circuitry
is provided along the DQ5 line, namely the test mode circuitry 136 and
multiplexer 40. Additionally, as noted above, the external testing device
can also determine if the test mode circuitry 36 has determined an error
by reading the test flag from the DQ7 line. Consequently, the external
testing device can determine the speed of the memory device 10 and
determine the data read from the memory device from the DQ5 line, while
also determining whether the test mode circuitry 36 has detected an error
from the DQ7 line.
Since the test data flag from the test mode circuitry 36 is provided at the
DQ7 line, the test data flag can be detected by the external testing
device at a time subsequently to the reading of the data from the DQ5
line. Therefore, while the test mode circuitry 36 and multiplexer 40
provide additional gate delays for the test data flag output on the DQ7
line, such delays are irrelevant to determining the speed the memory
device 10, since the speed can be determined from one of the other DQ
lines, e.g., DQ5.
The test mode circuitry 36 writes the same data values to the memory arrays
11A and 11B, compares the bytes of data, and outputs a low value if all of
the bits in the bytes match, as explained below. While rare, it is
possible that all of the data read from one of the memory arrays in a
given byte is erroneous, but that the test mode circuitry nevertheless
outputs a low or match signal for the data test flag indicating that the
memory device 10 passed the test. However, since the actual data written
to the array is also output from the DQ5 pad, the external testing device
can compare the data read on the DQ5 pad to the data which it previously
wrote to the device to determine if the two match. If they do not match,
then the testing device will recognize this error.
Referring to FIG. 3, the test mode circuit 36 includes four comparison
circuits 200, 202, 204, and 206. (Only two of the four comparison
circuits, comparison circuits 200 and 204, are shown in FIG. 3.) Each of
the compare circuits 200-206 includes a NAND gate 208 and a NOR gate 210
that each receive a signal DR representing data read from the memory
arrays 11A and 11B. The NAND gate 208 and the NOR gate 210 of the compare
circuit 200 receives the data read from the sub-arrays associated with DQ
lines DQ0, DQ2, DQ4 and DQ6, while the NAND and NOR gates for the compare
circuit 202 receives the data read from the sub-arrays associated with DQ
lines DQ1, DQ3, DQ5 and DQ7. In other words, the compare circuit 200
compares the even bits of a first 8-bit data word (DQ0-DQ7) to each other,
while the compare circuit 202 compares the odd bits from the first data
word to each other. The NAND gate 208 and NOR gate 210 of the compare
circuit 204 receives the data read from the sub-arrays associated with DQ
lines DQ16, DQ18, DQ20, DQ22 and DQ6, while the NAND and NOR gates for the
compare circuit 206 receives the data read from the sub-arrays associated
with DQ lines DQ17, DQ19, DQ21, DQ23 and DQ7. In other words, the compare
circuit 204 compares the even bits of a third data word DQ16-DQ23, while
the compare circuit 206 compares the odd bits of this data word. While
such comparison is divided by even and odd bits, other divisions of the
words or DQ lines could be employed. The compare circuits 204 and 206 also
compare 1 bit from the first data word (i.e., DQ6 and DQ7) to bits of the
third data word to reduce area on the die, as explained below.
The outputs of the NAND and NOR gates 208 and 210 are input to an exclusive
OR gate 212 in each of the compare circuits 200-206. The NAND and NOR
gates 208 and 210 both output a high value if all of their inputs are low,
and alternatively both output a low value if all of their inputs are high.
In response thereto, the exclusive OR gates 212 output a low value only if
both of their inputs are either high or low. Therefore, if any of the
inputs to the NAND or NOR gates are not equal to the remaining inputs,
then the exclusive OR gates 212 will not output a low value.
As is known, exclusive OR gates require a greater amount of surface area on
the die than NAND or NOR gates. Typically, prior on-chip testing circuitry
for semiconductor memory devices employed an additional comparison circuit
that compared two compared data words. For example, such prior systems
employed another comparison circuit, having at least one more exclusive OR
gate, that would compare the outputs from the exclusive OR gates 212 to
thereby compare the first data word with a third data word. Sinc | | |
