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Method of testing a protocol converter with the help of an identical converter and deactivating selection means for preventing asymmetry conversion
 
   
Document Number
US Patent 5968137
Issued Date
October 19, 1999
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Inventors
Ferraiolo; Frank D. (Essex Junction, VT)
Jung; Donald (Wappingers Falls, NY)
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Abstract
A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.
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Method of testing a protocol converter with the help of an identical converter and deactivating selection means for preventing asymmetry conversion - US Patent 5968137 Drawing
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Number of Claims:
11
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Published
October 19, 1999
Application Number
08/906,173
Filed
August 4, 1997
US Classification
710/5   341/4 341/75 341/76 341/78 710/11
Int'l Classification
H04L   29/06   (20060101)   H04L   12/26   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Aug 02, 1996 [DE] 196 31 289
USPTO Field of Search
710/5   710/11   709/230   341/4   341/75   341/76   341/78  
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6202108 - Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies - Owned by Bull S.A. (Louveciennes,FR)

A process for initializing a serial link between two integrated circuits comprises an initialized input-output port associated with each integrated circuit connected between a parallel bus and a serial link. Each port uses two clocks with different frequencies, a first higher-frequency clock for the serial link, called a transmitting clock, and a second lower-frequency clock for the signals arriving from the parallel bus, called a system clock. The process comprises the following steps: reinitializing the port with isolation of the receiving clock logic; reinitializing the transmitting clock logic; resetting the serial link between two ports; and initializing a two-way serial link by a looped process, either automatic or dependent on a microprocessor.

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