A delay circuit having standby state and active state and designed to output at least one signal obtained by delaying an input signal. The delay circuit comprises a storage circuit and at least one amplifier circuit. In operation, the storage circuit receives an input signal, generates a first voltage when the input signal is inverted, and generates a second voltage from a difference between the first voltage and a first supply voltage. The amplifier circuit amplifies the difference between the first voltage and the second voltage. The storage circuit includes at lease one constant-voltage generating section for generating the first voltage when the input signal is inverted, at least one constant-current generating section for generating a current proportional to the difference between the first voltage and the first supply voltage, and at least one capacitor having a first terminal set at the first supply voltage or a second supply voltage, and a second terminal charged to the first supply voltage while the delay circuit remains in the standby state and charged or discharged to the second voltage with the current generated by the constant-current generating section while the delay circuit remains in the active state.
A delay circuit includes a capacitor, a charging/discharging control circuit receptive of an input signal for controlling at least one of the charging and the discharging of the capacitor to set a delay time in accordance with a capacitance value of the capacitor, and a comparing circuit for comparing a voltage at a first terminal of the capacitor with a first reference voltage to produce an output signal which becomes inverted after the delay time when the voltage at the first terminal of the capacitor crosses over the first reference voltage during one of charging and discharging of the capacitor, and comparing a voltage at the first terminal of the capacitor with a second reference and producing an output signal which becomes inverted when the voltage at the first terminal of the capacitor is higher than the second reference voltage so that the delay time is reduced when the first terminal of the capacitor becomes short-circuited to an abnormally high voltage level.
A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C1 connected to the connection node MON. A differential amplifier compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.
An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state. The input circuit includes: four resistor elements serially provided between different fixed potentials; an input terminal connected to a connection point of two of the resistor elements; a switching transistor controlled to turn on and off by a voltage at a connection point of two of the resistor elements; a current supplying circuit outputting a supply current when the switching transistor is on and not outputting the supply current when the switching transistor is off; a constant voltage generating circuit receiving the supply current to output a constant voltage; a constant voltage output buffering circuit that brings its output into a high-impedance state when the switching transistor is off, and that receives the constant voltage to output a prescribed voltage to a connection point of two of the resistor elements when the switching transistor is on; a switching transistor controlled to turn on and off by a voltage between opposing ends of the resistor element; and a combinational circuit outputting identify signals based on combinations of on and off states of the two switching transistors.
A waveform generating circuit is provided which generates a modified triangular wave signal suitable for being input to a frequency modulation circuit such as a voltage-controlled oscillator (VCO). The waveform generating circuit includes a triangular generator, an offset generator for generating first and second offset component signals, a combiner for adding the triangular wave signal generated by the triangular wave generator and the offset component signals, and an output for delivering an output signal resulting from the addition by the combiner.
An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.
