An optical display element of one embodiment of the invention is disclosed that comprises a binary optical display element and a multiple-bit storage element to store a number of bits of a color intensity value to be displayed by the binary optical display element during a display period. Each bit is loaded from the multiple-bit storage element into the binary optical display element one or more times during the display period to achieve the color intensity value.

A system and method for reducing the phase difference between adjacent gray scale values employ compound data words. The compound data words include a first group of data bits and a second group of data bits. A display driver circuit is configured to provide display control signals causing each bit of the first group of data bits to be asserted on the display pixel for a coequal time period, and causing each bit of the second group of data bits to be asserted on the display pixel for a time period dependent on an associated significance of each bit. Optionally, the display driver circuit further includes a compound data generator configured to provide the compound data words. A method for asserting a compound data word on a display pixel includes the steps of asserting each bit of the first group of bits on the display pixel for a coequal time period, and asserting each bit of the second group of bits on the display pixel for a time period dependent on an associated significance of each bit.

The device comprising a video processing circuit (7) for processing the video data received, a correspondence memory (8) for transcoding these data, a video memory (9) for storing the transcoded data, the video memory being linked to column drivers (10) in order to control the column addressing of the plasma panel on the basis of column control words, a control circuit (11) for the line drivers (12), is characterized in that the control circuit for the line drivers simultaneously selects at least two successive lines during the transmission by the column drivers (10) of at least one of the bits of the column control words relating to one of these lines.

A controller (800) for a pulse width modulated display system. The controller (800) periodically determining the output of a light source by sampling the output of a light detector (808) an creating a smoothed approximation of the periodic waveform of the light source. A processor (806) in the controller (800) reads a base bit split sequence from a read only memory (804) and modifies the sequence by lengthening or shortening the bit periods described therein in order to compensate for the periodic variations of the light source. The modified bit split sequence is stored in two-port random access memory (802) where it is later accessed by both the processor (806) and a sequencer (304). The sequencer (304) reads the modified bit split sequence from the two-port random access memory (802) to determine when to load each bit of image data into a modulator an-ay. The processor (806) periodically reads the two-port random access memory (802) and further modifies the modified sequence contained therein to reflect additional waveform data collected by the detector (808).

A controller (15) for a display system (10) that uses a spatial light modulator (15) to display data formatted in bit-planes. The controller (15) receives at least some of the bit-plane data from a frame memory. It has local memory that buffers data transfer and stores data for bit-planes having multiple accesses, thereby increasing the bandwidth of data transfers from the frame memory (14) to the SLM (16).