 |
Description  |
|
|
BACKGROUND
This invention relates to an ultrasound system and method for processing
data. In particular, the method and system provide for processing,
transferring, and storing ultrasound data, control data, and other
information.
Ultrasound systems acquire, process, and store acoustic information. The
acoustic information is used to generate various types of images and other
data. Typically, ultrasound imaging systems include several dedicated data
processing structures, including one or more digital signal processors
(DSP) for processing the acoustic data and one or more microprocessors for
system control. The control microprocessors provide control instructions
to the data processing structures. The control instructions are generated
in response to operating system software, user interface input, and other
communication and control software. One or more separate memory blocks
provide bulk storage for CINE operations, storing acoustic data generated
by the various data processing structures. The memory blocks are designed
to support the specific volume and bandwidth of the real time data stored
in and retrieved from them. A separate memory is used for storing the
microprocessor software. As a result, the microprocessors do not have
direct and efficient access to acoustic data during real time operation of
the ultrasound system, and many different memories are required.
Another example of the separation of memories is the use of various display
refresh memory planes for generating an image. Ultrasound systems
typically employ separate display refresh memory planes for each of
combination control information, text and graphics information, waveform
information, and image information. The stored information is output from
each of these memories at a constant rate to update and refresh the
display. Due to different reconstruction and display requirements for the
different types of data, the refresh memory planes are separated. Text and
graphics information is generally constructed by a microprocessor and
written into the text and graphics refresh memory plane. Image and
waveform data are generally constructed by some combination of dedicated
hardware and DSP processing. The image and waveform data are then stored
in their respective memory planes. The output from the refresh memory
planes is combined and displayed.
One example of an ultrasound system is disclosed in U.S. Pat. No. 4,662,222
(the '222 patent). The '222 patent describes various models for
reconstructing an acoustic image using inverse scattering techniques.
Beginning at column 19, line 14, the system for generating the acoustic
image is described. The system includes a CPU and an array processor to
control the electronic system in accordance with the flowcharts shown in
FIGS. 6A-6F. At lines 25-28, the disclosure notes that "special purpose
computational hardware should be constructed to incorporate the flow
diagrams of FIGS. 6A-6F." The appendix of the '222 patent discloses a
program to solve the inverse scattering models by the array processor. The
CPU's control of the system to solve the inverse scattering models is then
described with reference to FIGS. 6A-6F.
Some ultrasound systems combine various memory structures and processing
structures. For example, U.S. Pat. No. 5,492,125 discloses two
multi-processors for processing acoustic data. The multi-processors share
a memory. The memory is accessed through a cross-bar. One multi-processor
receives acoustic data and partially processes the data. The partially
processed data is stored in the shared memory. The other multi-processor
obtains the partially processed data and completes the processing.
Multi-processors are used in systems other than ultrasound systems. For
example, multi-processors are used in personal computing. Various
multi-processors are known, such as Pentium Pro.RTM., Pentium II.RTM., and
other 686 class microprocessors that support multi-processing, and that
use single instruction multiple data processing. For use with graphics
intensive computers, interface devices such as the Intel.RTM. Accelerated
Graphics Port chip set are used to provide high speed interactions between
graphic accelerators, multi-processors and memories.
SUMMARY
The present invention is defined by the following claims, and nothing in
this section should be taken as a limitation on those claims. By way of
introduction, the preferred embodiment described below includes an
apparatus and method for processing ultrasound data. The apparatus
includes an interface operatively connected to a memory, a processor, a
source of acoustic data (such as a data bus) and a system bus.
In yet another embodiment, at least one peripheral connects to an
ultrasound apparatus. An interface adapter translates information
transferred between the peripheral and the ultrasound apparatus. The
adapter is powered from the ultrasound system. In preferred embodiments,
the adapter is used to connect non-standard peripherals to various
standard interfaces on the ultrasound apparatus.
Other embodiments are possible. Further aspects and advantages of the
invention are discussed below in conjunction with the preferred
embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an ultrasound imaging system, including
various peripheral components.
FIG. 2 is a block diagram of a data processing system of FIG. 1, including
various peripheral components.
FIG. 3 is a block diagram of one embodiment of a memory and an interface
device of FIG. 2.
FIG. 4 is a block diagram of one embodiment of an ultrasound acoustic data
acquisition path of FIG. 2.
FIG. 5 is a block diagram of one embodiment of a portion of the data
processing system of FIG. 2, including a video reconstruction data path.
FIG. 6 is a block diagram of a multi-processor system for use in the data
processing system of FIG. 1.
FIG. 7 is a block diagram of a peripheral connection.
FIG. 8 is a block diagram of one embodiment of a data transfer controller
of FIG. 2.
FIG. 9 is a flow chart representation of a processor functions.
FIG. 10 is a representation of a memory map of one embodiment.
FIG. 11 is a block logic diagram of one preferred embodiment for address
generation.
FIG. 12 is a representative memory map for an address generator table of
one preferred embodiment.
FIG. 13 is a block diagram of one preferred embodiment of a south bridge
configuration.
FIG. 14 is a representation of a memory map of one embodiment.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Referring to FIG. 1, a preferred embodiment of an ultrasound system
according to the present invention is generally shown at 20. The flexible
system 20 is described below, first with reference to the structure of the
system 20, and then with a reference to several examples of the operation
of the system 20. Other structures and uses of the system 20 are intended
to be covered by the claims, which define the invention.
Structure
General
The system 20 includes a transducer 22, a beamformer 24 and a data
processing system 26. The system 20 also includes various peripherals,
such as a hard disk drive 28, a removable media device 30 (e.g. a magneto
optical disk drive), a local area network 32, a display 34, a speaker 36,
a physio module 38, a microphone 40, a user interface 42 and other
external peripherals 44. The other external peripherals include video or
audio recording and playback devices, printers, cameras, and other
devices. The peripherals may include analog or digital video or audio
inputs and outputs. The physio module 38 preferably includes an EGG,
phono, pulse, respiration and one or more auxiliary DC-coupled input
channels (e.g. DC-A, DC-B, DC-C and DC-D). Preferably, the data processing
system 26 controls operation of the peripherals. The system 20 may include
no peripherals or any subset of these peripherals.
The data processing system 26 includes a centralized memory for storing
microprocessor code and data (software or algorithms) and concurrently
storing various subsystem data. The subsystem data includes acoustic image
data, video data, audio data, physio data, waveform data, text and
graphics data, and other subsystem data.
As used herein, the term ultrasound or acoustic image data encompasses data
derived from the transmission of acoustic energy and used to generate an
image or audio output in one or more of various modes, such as B-mode,
M-mode, color Doppler mode (velocity, variance or energy), spectral
Doppler mode (spectrum, derived waveform or audio) and other modes.
Ultrasound image data includes acoustic data from the beamformer 24 (e.g.
in phase and quadrature data or real value data), fundamental or harmonic
frequency based data, or acoustic data at various stages of processing
(e.g. detected data, filtered data, weighted data, thresholded data, video
data (compressed or uncompressed), combined data, and other processed data
derived from acoustic data from the beamformer). The type of ultrasound
image data (the stage of processing of the data) is referred to herein by
the type of processing, the source or the component used to process the
data. For example, harmonic data is ultrasound image data associated with
harmonic frequencies of transmitted fundamental frequencies. As another
example, beamforner data is ultrasound image data provided by a
beamformer. Ultrasound data includes ultrasound image data, audio data
(e.g. physio audio, microphone audio and VCR audio), waveform, physio,
video (compressed or uncompressed), text and graphics, patient and control
data used or generated in an ultrasound system.
The data processing system 26 also includes a microprocessor or parallel
microprocessors in a symmetric multiprocessing structure for controlling
the system and processing ultrasound image data stored in the centralized
memory. The microprocessor operates in response to or executes instruction
code and data also stored in the memory.
Based on control instructions from the data processing system 26, the
beamformer 24 generates electrical signals. The electrical signals are
applied to the transducer 22. The transducer 22 transmits acoustic energy
and receives echo signals. Electrical signals corresponding to the echo
signals are provided to the beamformer 24 from the transducer 22. The
beamformer outputs ultrasound image data, such as in phase and quadrature
(I and Q) data associated with a plurality of ranges along one or more
scan lines.
The data processing system 26 processes and stores the ultrasound image
data from the beamformer 24. Processing includes altering the data before,
after or as part of a reconstruction or scan conversion and output to the
display 34. For example, color Doppler information is detected from the I
and Q ultrasound image data, and the detected ultrasound image data is
stored. The stored ultrasound image data is then temporally or spatially
filtered or otherwise processed. The processed ultrasound image data is
also stored and output for reconstruction.
Other than the beamformer 24, one or more peripherals may provide
ultrasound data to the data processing system 26. The external peripherals
may also receive ultrasound data from the data processing system 26, such
as audio data or video ultrasound image data. The hard disk drive 28 and
the removable media device 30 provide and store software, ultrasound data
and other information for the data processing system 26. A local area
network (LAN) also supports the transfer of software or ultrasound data to
or from the data processing system 26. For example, operating system code,
patient data, parameter data, control data or image data is transferred.
The user interface 42 provides or receives information about the status of
the various user controls or displays (lights or other secondary displays
on the user interface 42 ). The physio module 38 provides patient
physiological data and event (trigger) information to the data processing
system 26, as well as the state of any user controls located on the physio
module 38. Various physio modules 38 may be used, such as an ECG or
respiration device. Data for operation of the physio module 38 is
communicated from the data processing system 26 or another source. The
microphone 40 allows for voice activated control of one or more user
selectable functions as well as the input of patient data, such as verbal
annotations. Information, such as ultrasound data, control and parameter
information, or patient information may be provided from any of these or
other peripherals.
Data Processing System
Referring to FIG. 2, a preferred embodiment of an ultrasound system
according to the present invention is shown generally at 50. As used
herein, an ultrasound system or apparatus 50 includes no, one or more
peripherals. Likewise, the ultrasound apparatus or system 50 may include
or exclude the beamformer 24. The system 50 preferably includes a data
processing system 52, the beamformer 24, and various peripherals. The
various peripherals include one or more of the hard disk drive 28, the
removable media device 30, the LAN 32, the display 34, the speakers 36,
the physio module 38, the microphone 40, the user interface 42, the
external peripherals 44, an analog video or audio peripheral 54 and any
other peripherals. Preferably, the beamformer 24 includes a multiplexer
for switching between receive and transmit processing. The beamformer 24
comprises transmit and receive beamformers. In this embodiment, the
receive beamformer is operatively connected to provide acoustic data, and
both transmit and receive beamformers receive and are responsive to
control and parameter information from the data processing system 52.
The data processing system 52 includes various ultrasound data paths and
system data paths. As used herein, a data path is one or more components
for receiving, processing or transferring data. Any of these various data
paths may be responsive to information from other data paths.
As used herein, the term "responsive to" is intended to broadly cover any
situation where a first component alters its operation in response to a
signal generated by a second component whether directly or indirectly.
Thus, the first component is said to be responsive to the second when the
first component responds directly to an output signal of the second
component. Similarly, the first component is responsive to the second if
intermediate components or processors alter or modify a signal of the
second component before it is applied as an input to the first component.
The data processing system 52 includes a system bus 56 and an ultrasound
data bus 58. An ultrasound acoustic data acquisition path 60, a
video/audio acquisition, processing and conversion path 62 (video/audio
acquisition data path 62), and a video/audio reconstruction and output
path 64 are connected to both the system data bus 56 and the ultrasound
data bus 58. These connections allow the transfer of ultrasound data or
system communication, control and parameter data between various
components of the system 50. The ultrasound data acquisition path 60 also
connects with the beamformer 24. The video/audio acquisition path 62
preferably also connects with the analog video/audio peripheral 54, the
microphone 40 and the video/audio reconstruction path 64. The video/audio
reconstruction path 64 also connects with the display 34 and the speakers
36. The system bus 56 also connects with the beamformer 24 and one or more
peripheral interfaces 66.
A data transfer control device 68 also connects to both the system bus 56
and the ultrasound data bus 58. An interface device 70 connects to the
data transfer controller 68, the system bus 56, a memory 72, and a CPU 74.
In one preferred embodiment, the various components of the data processing
system 52 are on three boards (a mother board and two daughter boards).
For example, the data transfer control device 68, the interface device 70,
the memory 72, the CPU 74 and the peripheral interfaces 66 are located on
the mother board, so that these components (e.g. the interface device 70
and the south bridge (see appendix C and FIG. 13) of the peripheral
interfaces 66 ) are grouped together. In this example, the ultrasound
acoustic data acquisition path 60 and the video/audio acquisition data
path 62 are on one daughter board, and the video/audio reconstruction path
64 is on the other daughter board. Other component partioning may be used.
The interface device 70 controls access to the memory 72. Preferably, the
interface device 70 is a quad port or other bridge device, such as the
Intel.RTM. 82443 LX, Intel.RTM. 440 BX, or a Via Technologies Inc. VT 82 C
597 PCI Accelerated Graphics Port (AGP) controllers. AGP is a
specification or protocol prepared by Intel.RTM.. The interface device 70
preferably includes a physical address generator for controlling the
memory 72. Other devices with more or fewer ports operating pursuant to
the AGP or other specifications may be used (e.g. three ports or a PCI
local bus protocol).
The interface device 70 interfaces between the memory 72, the CPU 74, the
data transfer controller 68 and the system bus 56 through a memory port
76, a CPU port 78, a data port 80 and a system port 82, respectively. As
used herein, a port is a connection or other interface for the transfer of
data to or from a component. Preferably, the CPU port 78 comprises a
microprocessor host interface with at least a 60 Mbytes/sec connection
(e.g. 64 bit data path at 96 MHz). Preferably, the memory port 76
comprises a 64 bit wide data path with a 64 or 96 MHz clock with at least
a 190 Mbytes/sec connection. The system port 82 comprises a PCI bus
interface with at least a 30 Mbytes/sec connection (e.g. 32 bit data path
at 32 MHz). The data port 80 comprises an AGP interface with at least a
100 Mbytes/sec connection (e.g. 32 bit data path at 64 MHz). The data port
complies with Intel's Accelerated Graphics Port Interface Specification
(revision 1.0 or later), but in alternative embodiments may employ any
data transfer mechanism meeting the bandwidth and requirements discussed
above or other appropriate requirements. Preferably, the data port 80
supports burst transfers of packets of ultrasound data with logical and
implicit sequential addressing of successive data values to facilitate
high through put and transfer efficiency.
The bandwidths discussed above are approximations and may vary as a
function of various factors, including programming and system
capabilities. Other effective bandwidths, bus widths, and clock rates may
be used. Preferably, synchronization signals are used for transferring
data between two different clock domains (e.g. 64 MHz to or from 48 MHz).
Alternatively, the interface 70 comprises other port designs, such as
supporting different protocols, different connection speeds or different
data widths. For example, a three port device without a data port 80 is
used. In this example, the ultrasound data bus is eliminated and
ultrasound data transfers are performed over the system bus 56.
The interface device 70 arbitrates between ports, translates interface
signals, buffers data, controls the memory 72, routes data between the
various ports and any sub-set of these functions. Preferably, the
interface device 70 is operable to transfer data between the CPU port 78
and the memory or system ports 76 and 82, and to transfer data between the
system or data ports 82 and 80 and the memory port 76. In alternative
embodiments, the interface device 70 transfers between the CPU and data
ports 78 and 80 or between the data and system ports 80 and 82.
The interface device 70 provides direct access to the memory 72 from the
CPU port 78, the data port 80, and the system port 82. The CPU 74 can
directly fetch instructions from memory 12 for execution, and data for
processing. The memory 72 is accessed by the CPU 74 as standard random
access memory in the CPU's 74 memory address space. Preferably, the access
is formatted for pipelined addressing of four or more quad words or other
sequences of data for improved throughput.
Accesses to the memory 72 from the system port 82 also support direct
memory read and write access through single read or write transactions on
the system bus 56 in the memory's 72 address space. Preferably, the system
port 82 of the interface device 70 supports and controls (e.g. arbitration
time out, parking and configuration cycle generation) burst transfers on
the system bus 56 according to the PCI local bus specification, where a
burst is comprised of multiple single transactions with implicit
sequential addressing after the first transaction.
Accesses to the memory from the data port 80 also support direct memory
access. Preferably, transfers on the data port 80 to or from the memory 72
employ pipelined transactions according to the AGP specification, where
the transaction request, size, and address are supplied to the interface
device 70 by the data transfer controller 68 over a set of sideband
signals. Preferably, the graphic aperture (memory window) is at least 256
Mbytes. The data transfer is subsequently performed by the interface
device 70 over the data port data bus in response to the request.
Transaction requests can be made concurrently with data transfers using
separate sideband data signals.
The memory 72 accepts data from or provides data to the CPU 74, the data
transfer controller 68 and the system bus 82. The memory 72 comprises a
synchronous DRAM (SDRAM) memory, such as a Texas Instruments' TMS 626162.
Alternatively, a SDRAM-II, Double Data Rate SDRAM (DDR SDRAM), a sync-link
DRAM (SL-DRAM), a RAMBUS DRAM (RDRAM), Direct RDRAM, Multi-Bank DRAM
(MDRAM), Cache Enhanced SDRAM (ES-DRAM), or a non-synchronous memory is
used. The memory 72 may comprise one or more memory components and one or
more modules, such as three 32 Mbytes DIMM modules. Each memory component
is associated with physical locations in the memory 72. Preferably, all of
the memory components operatively connect to and are controlled by the
interface device 70 (one memory). Less than all or other sources of
control may be used. The memory port 76 of the interface device 70
comprises a memory port 96 of the memory. More than one memory port 96 may
be used.
Referring to FIG. 3, the memory preferably comprises two memory banks 90
and 92 in one or more blocks 91. More or fewer banks 90, 92 or blocks 91
may be used. Preferably, each bank 90, 92 comprises one or more pages 94.
Referring to FIG. 2, the memory 72 provides storage for CPU code and data,
ultrasound image data from the data transfer controller 68, the CPU 74, or
the system bus 56, and other data provided from the CPU 74, the data
transfer controller 68, or the system bus 56. Other data may include text,
graphics or control plane data for display, audio data, control and
parameter data, messaging data, and patient information. Preferably, one
area or section of the memory 72 is dedicated to CPU code and data and
interprocessor communication and control data. As shown in FIG. 10, a 4 GB
address range is used, but other ranges may be used. From 512 Kbytes to 1
Mbyte, legacy components (DOS compatibility) are located in the system
addresses space. In FIG. 10, BIOS represents the system boot and
configuration ROM occupying 128 kB within the 512 kB to 1 MB range and 1
MB at the top of the 4 GB address range. Resources connected to the system
bus 56 are accessed in the 2 GB to 40 GB 20 MB range. Preferably, at least
64 Mbytes of memory is dedicated to acoustic, waveform, text and graphics,
and video storage. Other memory allocations and maps may be used.
The CPU 74 is a programmable processor operable to run operating system,
user interface, communication, control, applications and ultrasound data
processing software or any sub-set of this software. Preferably, the CPU
74 is a 64 bit single instruction multiple data processor (SIMD), such as
Intel's Pentium II.RTM. processor (e.g. 350 MHz with a 100 MHz frontside
bus and 512 Kbytes of L2 cache integrated in a slot 1 single edge contact
cartridge). As used herein, single instruction multiple data processors
are processors capable of applying a single instruction on multiple data,
such as in parallel processing paths. Furthermore, a multi-media extension
(MMX) SIMD processor may be used. Other processors may be used, such as by
other manufacturers, with 32 bits, or without SIMD capability.
Preferably, a cache memory is internal to and managed by the CPU 74, but in
alternative embodiments the cache memory may reside on a host-bus and be
managed by the interface device 70. Other embodiments may contain both CPU
internal cache and host bus cache which are managed by either the CPU 74,
interface device 70, or both. The cache memory reduces transfers to memory
72 on the CPU port 78 and improves performance for instructions and data
that are repeatedly used. The cache memory of the CPU 74 temporarily
stores ultrasound data, such as image data, for processing by the CPU 74.
Upon completion of the processing, the ultrasound data is stored in the
memory 72. Additional ultrasound data is then stored in the cache of the
CPU 74 for undergoing the same processing. Furthermore, the cache memory
may contain both instructions for execution by the CPU 74 as well as
ultrasound data, such as image data.
The host bus connects to the CPU port 78 of the interface device 70. The
CPU 74, using the host bus, obtains software data (instruction code) from
the memory 72 for execution. The CPU 74 operates or executes pursuant to
the software data.
In an alternative embodiment, the CPU 74 comprises two or more
microprocessors. Referring to FIG. 6, two symmetric processors 100 and 102
are shown. Preferably, the processors 100 and 102, such as Intel's
Pentium.RTM. processors, operate pursuant to a symmetric multiprocessing
protocol. For example, Intel's multi-processor specification (version 1.4
May 1997) defines the use. Preferably, a master slave relationship or any
other hierarchy or geometry limitations on processing and communications
is not created | | |
