A device manufacturing method prevents damage from plasma charging and vertical cross talk. The method comprises the steps of forming an insulating layer over a substrate that has a MOS device and source/drain regions already formed thereon. The insulating layer is formed by a non-plasma operation so that plasma damage is avoided. Thereafter, a conductive layer is formed over the substrate. The conductive layer is used to channel away excess charges produced during subsequent plasma operations, thereby balancing electric potential and preventing damage to the device from current flow. Subsequently, an inter-layer dielectric layer is formed over the conductive layer, and then the inter-layer dielectric layer, the conductive layer and the insulating layer are patterned to form an opening that exposes the source/drain region. Finally, a conventional method is used to form another insulating layer over the exposed conductive layer in order to prevent direct contact with subsequently formed metallic contacts inside the opening.

A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an initial oxide layer which is removed from the silicon wafer by a hydrogen baking step. A new oxide layer or nitrided oxide layer is formed by thermal growth on the silicon wafer surface. A portion of the new oxide layer is removed by hydrogen annealing. A MOSFET can be created by forming a gate electrode structure on a high-k dielectric material deposited on the new oxide layer.

An aspect of the present invention includes; a silicon oxynitride film having an oxynitride layer which is formed on at least the surface of a silicon substrate and in which nitrogen atoms are in a three-coordinate bond state, and a silicon oxide layer which is formed between said oxynitride layer and said silicon substrate.

An SOI substrate having a silicon layer formed on an embedded oxide layer is prepared at a step ST11. An exposed surface of the silicon layer is thermally oxidized for forming a thermal oxide film at a step ST12. The thermal oxide film, enclosing a defect in the silicon layer, is formed in a shape on or to which the defect is reflected or transferred. At this time, thermal oxidation is so executed that the transferred part of the thermal oxide film is in contact with the embedded oxide layer. The SOI substrate is dipped in a hydrofluoric acid solution at a step ST13. Thus, the thermal oxide film is removed while the embedded oxide layer is eroded through the part in contact with the thermal oxide film. According to this inspection method ST10, the defect is reliably transferred to the embedded oxide layer through the thermal oxidation step ST12, whereby it is possible to evaluate an inner defect undetectable/unevaluative by a conventional inspection method. Thus, the defect of the silicon layer is inspected/evaluated for obtaining an SOI substrate of high quality and improving the manufacturing yield of a semiconductor device.

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800.degree. C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.