In a semiconductor device constituted using a borderless contact technique, for example, when a wiring layer with a damascene structure is connected to its underlying contact portion, a trench connecting with the contact portion is formed in the second interlayer insulation film. After that, the contact portion protruded from the bottom of the trench is selectively etched to flatten the bottom of the trench to remove a very small recess from that bottom of the trench which corresponds to a contact face between the contact portion and wiring layer. Thus, both a barrier metal layer and a metal layer for forming the wiring layer can be formed in the trench with higher reliability and accordingly the wiring layer and contact portion can be brought into reliable contact with each other. In a DRAM using a simple stacked capacitor, the storage electrode and plug portion can be put into reliable contact with each other.
A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.
A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening. The line trench is etched further into the dielectric layer until metal plug is reached. The trench is then filled with metal, such as aluminum-copper or copper and the excess is removed by chemical-mechanical polishing. Thus, a borderless and self-aligned interconnect comprising plug and metal line is formed.
Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line, thereby preventing halation caused by irregular reflection during exposure on the second photo resist because the second insulating layer has a less difference in thickness, and suppressing decrease in the exposed area of the first conductive line caused by extension of the first opening.
A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.
Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
