A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

An image data transfer system and method enable scan time and transfer time of the image data to be adjusted appropriately without lacking a part of the image data, suitable for low price. A data segmentation device segments the image data from a scan device into high order n bits and low order (N-n) bits, subsequently, transferring the high order n bits toward a data transfer device at the same time when the scan device scans a manuscript, and transferring the low order (N-n) bits toward a memory device. The data transfer device transfers the high order n bits of the image data toward a personal computer at the same time when the scan device scans the manuscript. The memory device stores therein the low order (N-n) bits of the image data temporarily. Furthermore, the data transfer device scans the low order (N-n) bits of the image data from the memory device to transfer toward the personal computer after transfer of the high order n bits.

A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.