A controller module is coupled to a plurality of application modules over a backplane. The backplane comprises a differential bus(s) having a TX and RX data signal, a differential clock signal, and a single ended collision detection line. The application modules transmit data to the controller module. The controller module retransmits a recovered version of the data back to the application modules over the collision detection line. Each application module compares the retransmitted data bits with the data bits it originally transmitted. If the data is not the same, a collision has occurred and the application module removes itself from the bus. If the data is the same as that transmitted originally, that particular application module continues to transmit on the bus. Metastability at the controller module's differential receiver enables multiple differential transmitters to be on the differential bus at the same time.

An application module, that is part of an electronic assembly including a controller module, is coupled to a backplane bus structure. The backplane comprises a differential bus(s) having a TX and RX data signal, a differential clock signal, and a single ended collision detection line. The application module comprises differential bus transceivers that are controlled by differential bus control logic on the application module. The control logic compares data bits received over a collision detection line with the data bits the application module originally transmitted. If the data is not the same, a collision has occurred and the control logic places the bus transceivers into a high impedance state. A data packet controller on the application module can only detect certain types of collisions that occur in the single ended environment. The control logic enables the data packet controller to recognize a collision that it normally would not.

A data exchange system includes at least one transmitting agent, at least one receiving agent, and a plurality of data links each having a crossbar coupling respective transmitting agents and receiving agents. A stream of data packets including at least one Order Critical Flow of data packets having a critical order to be sent from the transmitting agent to the receiving agent is divided for transmission among the plurality of data links. Multiple Order Critical Flows between the transmitting agent and the receiving agent are possible and the packets within such Order Critical Flows can be intermixed for transmission (along with packets from other Non-Order Critical Flows). The packets are transmitted over the data links so that packets from the same Order Critical Flow are transmitted over the same data link (while packets from that Order Critical Flow are in the Transmit Link Queue) and the packets are sequentially numbered, based upon the time when the packet was first received (and not the link over which the packet was received) upon the beginning of receipt by the receiving agent and reassembled by the receiving agent into a stream of data packets in accordance with the numbering sequence, thus maintaining the order of all Order Critical Flows.

The network interface device has multiple blocks having internal connections, and has an external interface. The network interface device is configurable to reroute one or more of the internal connections onto the external interface to allow testing of the blocks of the device. The external interface may also be coupled so as to pass data between the network interface device and higher levels in a network protocol stack. In an exemplary embodiment a network interface device has a media access controller (MAC) and a physical layer device (PHY). An internal media independent interface (MII) between the MAC and the PHY may be selectively rerouted to an external MII for independently testing operation of either the MAC or the PHY.

A method and apparatus for reliable interrupt reception over a buffered bus utilizes a non-delayed non-posted write transaction to write data over the bus from a peripheral device to host memory. Because there is no buffering delay in a non-delayed non-posted write transaction, at the completion of the write cycle the peripheral knows that the write transaction is complete and then sends an interrupt request to the host processor requesting the host processor to service the interrupt and process the contents of the host memory.