An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.

A semiconductor device fabrication method of the present invention includes: a step of forming an insulation film on a semiconductor substrate on which a plurality of gate electrodes are formed; a step of applying SOG of HSQ type on the insulation film; a first firing step of firing the resulting substrate at a first temperature in nitrogen atmosphere; a step of forming an oxide film on the SOG of the HSQ type by a CVD method; a step of forming contact holes to expose the semiconductor substrate by removing the insulation film and the SOG of the HSQ type and the oxide film in the regions among a plurality of the gate electrodes; and a second firing step of firing the resulting substrate after the first contact hole formation at a second temperature higher than the first temperature.

An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400.degree. C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.

In manufacturing a barrier-forming film, a vapor-deposited inorganic oxide film is provided on a face of a substrate film. An annealing treatment is applied to the substrate film having said vapor-deposited inorganic film. The substrate film is a resinous film which selected from a group consisting of polyesters, polyamides and polypropylenes. The annealing treatment includes a heating treatment carried out at a temperature within the range from 55.degree. C. to 150.degree. C. in order to cause thermal shrinkage of the substrate film and to increase density of the vapor-deposited inorganic oxide film. The vapor-deposited inorganic oxide film includes a vapor-deposited silicon oxide film or a vapor-deposited aluminum oxide film.