Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the-hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below lmtorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
CROSS REFERENCE
This is a continuation of application Ser. No. 08/753,991, filed Dec. 3, 1996, now U.S. Pat. No. 5,889,328, which is a continuation of application Ser. No. 08/346,208 filed Nov. 22, 1994, now U.S. Pat. No. 5,585,673, which is a divisional of application Ser. No. 08/125,107 filed Sep. 21, 1993, now U.S Pat. No. 5,426,330, which is a continuation of application Ser. No. 07/841,967 filed Feb. 26, 1992, now U.S. Pat. No. 5,300,813.
A semiconductor device has an active element structure formed on a semiconductor substrate. The active element has a connection region formed on a surface of the semiconductor substrate. An insulating film is formed on the semiconductor substrate. A connection hole is formed in the insulating film, and has a bottom connected with the connection region. An interconnect trench is formed in the insulating film, and has a bottom connected with the connection region. A first conductive film is filled in a first region ranging from the connection region in the connection hole to a first height, and is composed of an alloy containing CoW or NiW. A second conductive film is formed in the interconnect trench, and is electrically connected with the first conductive film.
A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.
A MOSFET in which the gate electrode is formed of a polycrystalline silicon film, a silicon nitride film having a nitrogen surface density of lens than 8.times.10.sup.14 cm.sup.-2, and a tungsten film--these films formed one upon another in the order mentioned. The gate electrode thus formed, serves to shorten the delay time of the MOSFET.
Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.
A method of forming tungsten films on oxide layers is disclosed. The tungsten films are formed on the oxide layers by treating the oxide using a silane based gas mixture followed by the thermal decomposition of a W(CO).sub.6 precursor. After the W(CO).sub.6 precursor is thermally decomposed, additional layer of tungsten may be optionally formed thereon from the thermal decomposition of tungsten hexafluoride (WF.sub.6).
