Direct connect carrier for testing semiconductor dice and method of fabrication

Claims

What is claimed is:

1. A system for testing a semiconductor die, comprising:

a base configured to retain the die;

an interconnect on the base comprising a substrate, a plurality of first contacts on the substrate configured to electrically contact a plurality of second contacts on the die, and a plurality of input/output pads on the substrate in electrical communication with the first contacts, the first contacts and the input/output pads comprising wear resistant contact layers; and

a socket configured to receive the base comprising a plurality of electrical members in electrical communication with test circuitry, and configured to mechanically and electrically engage the input/output pads with the interconnect on the base, to provide a plurality of electrical paths for applying test signals directly from the electrical members to the input/output pads, without an electrical connection on the base.

2. The system of claim 1 wherein the wear resistant contact layers comprise a material selected from the group consisting of palladium, tungsten, platinum, alloys of palladium, alloys of tungsten, and alloys of platinum.

3. The system of claim 1 the wear resistant contact layers comprise a metal silicide.

4. The system of claim 1 further comprising a polymer layer attaching the interconnect to the base.

5. The system of claim 1 wherein the die comprises a chip scale package.

6. A system for testing a semiconductor die, comprising:

a base configured to retain the die;

an interconnect on the base comprising a substrate, a tape attached to the substrate, a plurality of microbump contacts on the tape configured to electrically contact pads on the die, and a plurality of input/output pads on the tape in electrical communication with the microbump contacts, the microbump contacts and the input/output pads comprising wear resistant contact layers; and

a socket configured to receive the base comprising a plurality of electrical members in electrical communication with test circuitry, and configured to mechanically and electrically engage the input/output pads with the interconnect on the base, to provide a plurality of electrical paths for applying test signals directly from the electrical members to the input/output pads, without an electrical connection on the base.

7. The system of claim 6 wherein the socket comprises a mechanism for mechanically biasing the electrical members into engagement with the input/output pads.

8. The system of claim 6 wherein the die comprises a chip scale package.

9. The system of claim 6 further comprising a polymer layer attaching the interconnect to the base.

10. The system of claim 6 wherein the electrical members comprise spring contacts and the socket comprises a mechanism for mechanically biasing the electrical members into engagement with the input/output pads.

11. The system of claim 10 wherein the contact layers comprise a material selected from the group consisting of metal silicide, palladium, tungsten, platinum, alloys of palladium, alloys of tungsten, and alloys of platinum.

12. A system for testing a semiconductor die comprising:

a carrier configured to hold the die, the carrier comprising a base, an interconnect on the base comprising a substrate, a first contact on the substrate configured to establish temporary electrical communication with a second contact on the die, and an input/output pad on the substrate in electrical communication with the first contact, the first contact and the input/output sad comprising a contact layer comprising a material selected from the group consisting of metal silicide, palladium, tungsten, platinum, alloys of palladium, alloys of tungsten, and alloys of platinum; and

a testing apparatus comprising a socket configured to receive the carrier and an electrical member on the socket in electrical communication with test circuitry, the electrical member comprising a spring contact configured to mechanically and electrically engage the input/output pad with the interconnect on the base, to provide an electrical path for applying test signals directly from the electrical member to the input/output pad, without an electrical connection on the base.

13. The system of claim 12 wherein the die comprises a chip scale package.

14. The system of claim 12 wherein the socket comprises a mechanism for mechanically biasing the electrical member into engag