To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inverter circuit and an inverter circuit connected in series. The plurality of digital data latch circuits has a first N-channel Tr and a second N-channel Tr of which the sources or the drains are connected in series, a P-channel Tr, and a data holding circuit. The clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal and a start pulse to thereby feed the timing signal to the register circuit neighboring a register circuit and to a gate electrode of the first N-channel Tr and the P-channel Tr feeds a first electric voltage to the data holding circuit in accordance with a Res signal inputted to the gate electrode. The second N-channel Tr then takes in digital data on the basis of the timing signal to thereby output the digital data to the source or the drain of the first N-channel Tr. The timing signal outputted from the register circuit neighboring a register circuit is fed to the gate electrode of the first N-channel Tr.

In the conventional liquid crystal display, there exists a problem in display that shortage in voltage applied to a liquid crystal and crosstalk occur because of delay in waveform of a common potential Vcom. A liquid crystal display has a drive circuit for applying a gate potential Vg having a High potential setting a gate line 1 to a selection level and a Low potential setting the gate line to a non-selection level to the gate line 1 of a display panel, comprises a common potential generation circuit for applying a common potential Vcom inverting to a high potential or a low potential for each horizontal scanning period to a common electrode 10 of the display panel, an auxiliary electrode connected to a picture element electrode 6 through an auxiliary capacity 7 is provided, the auxiliary electrode is connected to a common line, Low potential changed synchronizing with the high potential and low potential of the common potential Vcom and with respect to a potential difference between the second voltage and the common potential, the potential difference at the high potential of the common potential is equal to that at the low potential of the common potential.

To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inverter circuit and an inverter circuit connected in series. The plurality of digital data latch circuits has a first N-channel Tr and a second N-channel Tr of which the sources or the drains are connected in series, a P-channel Tr, and a data holding circuit. The clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock Signal and a start pulse to thereby feed the timing signal to the register circuit neighboring a register circuit and to a gate electrode of the first N-channel Tr and the P-channel Tr feeds a first electric voltage to the data holding circuit in accordance with a Res signal inputted to the gate electrode. The second N-channel Tr then takes in digital data on the basis of the timing signal to thereby output the digital data to the source or the drain of the first N-channel Tr. The timing signal outputted from the register circuit neighboring a register circuit is fed to the gate electrode of the first N-channel Tr.

An active matrix type liquid crystal display apparatus includes a display pixel unit including a plurality of pixels arranged in a matrix; a data signal driving circuit for outputting a gray-scale voltage control signal to the pixels and having a pulse width in accordance with gray-scale information of display data, a scan signal driving circuit for outputting at least one of an active voltage and inactive voltage to the pixels, and a gray-scale voltage selecting circuit for outputting a gray-scale voltage to the pixels. The gray-scale voltage in increased and decreased in accordance with time. Each of the pixels includes a liquid crystal cell and a switching element having a drain terminal, a common terminal and a gate terminal. The gate terminal is connected to the data signal driving circuit through a gate electrode, the common terminal is connected to the scan signal driving circuit through a common electrode, and the drain terminal is connected to the gray-scale voltage selecting circuit through a drain electrode.

An active matrix display device comprising an integrated peripheral driver circuit improved in image quality, provided in such a constitution that the feed through voltage .DELTA.Vs is set lower than the voltage Vgr necessary for realizing a single gradation. In this manner, a stable gradation display is obtained without being influenced by the feed through voltage .DELTA.Vs even when the fluctuation in the characteristics of the thin-film transistors provided in active matrix circuit may fluctuate the .DELTA.Vs.