An apparatus and method for supporting multiple types and configurations of random access memory devices in a single dual in line memory module (DIMM) socket architecture is provided. Typically, this architecture allows a user to select either SDRAM or EDO to be located in the socket(s) without substantially altering the connectivity between circuit components. A switching arrangement, that can be either active switches or fixed circuit traces, is used to selectively interconnect various control and addressing functions inherent in the microprocessor to appropriate pins of the memory device socket(s) depending upon whether EDO or SDRAM is used. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.
A wiring board according to the present invention includes a mounting region in which memories having different storage capacities can be mounted. The mounting region has: first wires for, when a first memory is mounted, making it possible to access all the addresses of the first memory; and second wires for, when a second memory having a storage capacity different from that of the first memory, making it possible to access to all the addresses of the second memory. For this reason, before an electronic device on which the wiring board is mounted is shipped, a memory mounted in the mounting region can be selected depending on the demand of a user.
An apparatus and method for supporting multiple configurations/sizes of random access memory devices in a single socket architecture is provided. In general, the address lines of the microprocessor are interconnected through a multiplexer and buffer arrangement that divides the address lines into two groups. The two groups of address bits, so divided, are selectively routed to predetermined pin connections of a dual in-line memory module (DIMM) socket that interconnect with predetermined address lines of the resident random access memory. The address bits are transmitted to the pin connections during each of the row address cycle and the column address cycle of the memory. The interconnections between the multiplexer/buffer and the random access memory are arranged so that a variety of standardized address pin configurations are supported by the same socket.
A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.
A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2,5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules.This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.
The present invention incorporates a technique that enables the processing of memory requests without requiring memory devices that support a request identifier (ID). The present invention maintains an association between a request identifier and a first memory request issued by a requestor and directed to a memory location. The first memory request contains an address corresponding to the memory location. A memory device corresponding to the address is selected. A second memory request without the identifier is issued to the selected memory device to access information stored at the location. The information is received from the memory device and associated with the request identifier.
