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Description  |
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FIELD OF THE INVENTION
The present invention is related to integrated circuit system technologies according to a novel Document-Instruction-Set-Computing (DISC) principle. More specifically, the present invention not merely defines the core functions for a baseline
DISC single chip integrated circuit, it equally set sufficient evolution guidelines for future generations of scalable DISC microprocessors capable of wide range of real-time performance. In particular, these novel DISC microprocessors can effectively
perform distributed document storage, processing and retrieval operations for systems, services, and applications including, but not limited to, personal communication systems, interactive database retrieval, HDTV, object-oriented systems and functions,
and multimedia computing devices.
BACKGROUND OF THE INVENTION
Digital signal coding, storage, retrieval, control, and processing of document data types in real-time represents the most time-critical functional component for many of the emerging computing, communication, and storage systems or devices. For
almost all of the document signal processing technologies which being developed to date, single or plurality of host processors or coprocessors means, in conjunction with additional hardware, firmware, or software means, are proposed according to the
existing complex-instruction-set-computing (CISC) or reduced-instruction-set-computing (RISC) principles.
These CISC or RISC host processing or coprocessing techniques can partially improve the performance of specific data subsystems, such as encoding multiple algorithms, managing memory or display devices, and adapting to existing DOS, OS2, WINDOW,
NT, or UNIX application and system environments. Typically, they can be readily implemented either in hardware, firmware, or software means embedded with custom integrated circuit, digital signal processor, or application specific integrated circuit
(ASIC's). Though practical, the speed and performance of these technologies are severely limited by the overall system throughput, and the run-time architectural supports for processing; networking; program control; and memory management imposed by the
CISC and RISC data computing principles.
Since CISC and RISC technologies have primarily invented to optimize the run-time data computation performance for fixed or floating point data operations, run-time procedure and data are typically coded, stored and retrieved in specific file
format from local or remote disk storage. Therefore, CISC and RISC computing devices becomes insufficient to meet real-time performance when it is required to interactively manipulate, retrieve, and process variable-size document data types, and to
provide direct real-time architectural support for distributed processing and database programming environment. For example, please refer to U.S. Pat. No. 5,056,154 to Aono, U.S. Pat. No. 5,047,953 to smallwood, U.S. Pat. No. 5,010,495 to
Willetts, and U.S. Pat. No. 4,899,148 to Sato.
While the aforesaid patents teach individual method and apparatus for compressing and decompressing the binary document image data, improving the document data frame memory subsystem performance, and enhancing the visual quality for display or
printout of the decompressed document image, none of aforesaid patents have ever directed themselves to the concept and structure of a novel method and apparatus for more generalized computing platform which would interconnect all the data processing
machines for enterprise, consumer, and communications, and allow individuals to create, augment, select, interpret, retrieve, update, and present multiple forms of compound document data, including annotated descriptions of sound, image, graphics, and
live video sequence in a coherent and effective system architecture which would automatically adjust to each individually available processor and memory bandwidth, capable of communicating in multiple bandwidths to traverse through wide ranges of
networks, prioritize each individual complex document data types, and allow for optimum performance for complex document data interpretation and processing.
More significantly, although all these prior arts have shown CISC and RISC can be extremely suitable for traditional computation-intensive application and programming environments. None of the aforesaid patents have directed themselves to the
concept and structure of broadening the scope, and to develop a new computing facility. This new computing platform can not only interconnect the regular computers and workstations, but it can also interconnect many other desktop data equipment,
including but not limit to, copy machines, scanners, fax machines, printers, televisions, camcorders, telephones, VCR's, CD players, cameras, sensors, or any other consumer and personal communication devices in a totally integrated system and database
environment. Consequently, in this novel integrated computing environment, complex document data manipulation, storage, and retrieval gain the highest priority, and achieve the best performance as comparing to traditional data computation tasks, and
regular computers and workstations would become a subset of this novel distributed computing platform.
DISC architecture offers a totally new distributed computing platform. Distinguish from all the prior arts which have adapted the traditional CISC or RISC computing discipline, DISC provides new methods and apparatus to organize a plurality of
complex document data types, DISC also streamline, optimize and preschedule the document instruction clusters, and provide parallel or pipeline execution for these instructions. DISC further provide hardware architectural supports to efficiently execute
high-level programming and database language constructs, and to facilitate CISC or RISC application coprocessor for traditional DOS or UNIX applications. Finally, DISC provide distributed object-oriented operating-system interface !to support
supplemental execution of traditional DOS or UNIX application tasks with the real time DISC document signal processing.
OBJECTS OF THE INVENTION
Accordingly several objects and advantages of my invention are:
An object of the present invention is to define an integrated document computing architecture which can accommodate communications, storage, and retrieval, of all digitally-coded or algorithmic complex document data types.
Another object of the invention is to provide a novel integrated system architecture which is flexible and allows the control and communications among copy machines, scanners, fax machines, printers, camcorders, televisions, telephones, VCR's, CD
players, cameras, sensors, or any other consumer and personal communications data processors, as well as desktop data processors such as computers and workstations.
A still further object of the present invention is to provide for a novel process architecture which allows for direct hardware support in compression, bandwidth management, program control, instruction streamlining and prescheduling, parallel or
pipeline execution, run-time memory and database management, decompression, display and printout, and other time-critical functions for manipulation, storage, and retrieval of complex document data objects in high-level programming and database language
architecture.
A still further object of the present invention is to provide for a novel process architecture which not only allows for digital coding techniques, but also can interface with traditional analog storage or transmission techniques.
A still further object of the present invention is to provide for a novel process architecture which allows the human users to interface with application program and database, and to select the appropriate document data types media combination
either before or during the communication session.
A still further object of the present invention is to provide for a novel process architecture which not only allows for the most optimized system performance for complex document data types, but also can directly execute traditional
computation-intensive application programs using a CISC or RISC application coprocessor.
A still further object of the present invention is to provide for a novel process architecture which allows for an optimized operating system for complex document data types, and accommodate traditional UNIX, DOS, or other traditional desktop
operating systems.
Further objects and advantages of the present invention will become apparent from a consideration of the drawings and ensuing description of it.
SUMMARY OF THE INVENTION
Our present invention, DISC (Document-Instruction-Set-Computing) architecture, offers new computing discipline optimized for real time data manipulation and interpretation for compound document related applications. This is totally distinguished
from all prior arts which have adapted the traditional CISC or RISC architectural discipline, which are best optimized for real time data computation. DISC provides new methods and apparatus to organize, store, retrieve, update, and present a plurality
of compound document data types. DISC also streamline, optimize, and preschedule these document instruction clusters, and provide parallel or pipeline execution for these instructions. DISC further provides hardware supports for run-time memory and
database management, program control, preprocessing and post processing, compression and decompression. DISC can directly query document data from either memory, file, or databases. DISC further sport CISC or RISC application coprocessor to perform
traditional DOS or UNIX or alike applications. Finally, DISC provides object-oriented operation system and database interface which can provide concurrent execution of DISC, DOS and UNIX operations.
FIGS. 2A and 2B show the architectural principle of DISC. Contrary to a traditional RISC or CISC architecture, the data processors and memory system are completely optimized to facilitate variable sized block oriented data instead of the
traditional bit-oriented data streams. To be more specific, data information are organized according to selective internally reconfigurable block format, wherein these internal format can accommodate various processor configurations as well as data
throughput. A scalable smart memory system architecture and memory management unit also provides the programmable data block addressing, frame memory management, and associative block search.
In addition, DISC Instruction sets can be statically compiled into a set of system look-up tables (SLUT's). Based upon the run time bandwidth constraints caused by either network congestion or application request, the DISC instruction processor
can prefetch a group of such DISC instructions, and designate them with various functional units for parallel or pipeline execution. Comparing to the more traditional cache or virtual memory techniques widely used in the existing RISC or CISC computers,
the SLUT technique employes intelligent fast associative search scheme, and is able to simultaneously perform prescheduling, compilation, linking, assembling, dereferencing, and issuing instructions for run-time execution, program control, and memory or
database management functions.
In a DISC architecture, a scalable smart memory system is connected to the functional units and scalable formatter, which can access, store, and transfer blocks of document data based on the selective internal format.
In FIG. 3, DISC architecture also illustrate an embedded RISC or CISC co-processor element in order to directly execute the bit oriented application programs in DOS, Window, NT, Macintosh, OS2, UNIX, or alike. In a more preferred embodiment,
DISC can include a real time object oriented operation system wherein concurrent execution of the application program and real time DISC based document computing can be performed.
DISC architecture provides a single computing platform to support a plurality of supplemental document data types including but not limited to, live motion video, voice, music, still image, and animated graphics. Consequently, it becomes
feasible to digitally integrate copy machine, scanner, fax machine, printers, slide projectors, camcorders, television, computers, cameras, telephones, answering machines, and alike, with human users and traditional application program.
BRIEF
DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the pictorial illustration of a typical document instruction set computing (DISC) environment.
FIG. 2A and FIG. 2B show the core DISC integrated circuit system architecture in accordance with the present invention.
FIG. 3 illustrates the major functional operations for a DISC (document instruction set computing) integrated circuit in accordance with the present invention.
FIG. 4 illustrates the architecture and organization of the present invention and a single chip integrated circuit implementation for compound document computing.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
1. General Discussion
Referring now to the drawings wherein like reference numerals refers to similar or identical parts throughout the several views, and more specifically to FIG. 1 thereof, there is shown a pictorial representation of a novel integrated circuit DISC
(document instruction set computing) system apparatus. There is also shown a pictorial illustration depicting most of the popular business or consumer electronic apparatus relating to computer, communications, and entertainment presently available for
the homes or offices. These include a copier, printer, scanner, fax machine, telephone, camcorder, CD player, television, personal computer, and personal communications devices.
It is Applicant's intention to disclose a unified system method towards integrated circuit design of all future interactive document-oriented personal communications and/or computing systems.
It is also Applicant's intention to illustrate the architecture design of a DISC apparatus according to this unified system design method.
Furthermore, the DISC system apparatus allows for compatibility with all existing business and consumer electronic apparatus. DISC user/operator can control, and utilize the functions of each electronic apparatus by means of the DISC system
apparatus. The DISC apparatus, being of compact size and shape, similar to that of a VCR, desktop or notebook PC, remote controller, or smaller, can interconnect with all local or remote electronic apparatus, and permit them to function complimentary
with each other.
It is yet another Applicant's intention to further substantiate a distributed system architecture for DISC, in which a plurality of DISC's can either locally or remotely communicate with each other and other non-DISC apparatus. Regardless of
whether other apparatus were analog, digital, hardware, software, or algorithm, the DISC's can encode, forward, decode, and interpret automatically to the available bandwidth, in a totally integrated system environment.
It is beyond the scope of the present invention to detail all the exact nature and coordination of the system, but details of these operations have been previously disclosed on a copending application, entitled "Methods and Apparatus including
System Architecture for Multimedia Communications", filed Sep. 20, 1991, Ser. No. 07/763,451.
2. General Introduction of Disc
FIG. 2A and FIG. 2B illustrates the core architecture, operation, and methodology for the design and implementation of a DISC 112 integrated circuit computer and communications system.
DISC 112 makes it possible to retrieve, interpret, substantiate, correspond, and maintain a multitude of compound document objects over a wide range of communications networks.
Prior arts in accordance with traditional RISC or CISC methodologies have shown plentiful methods and apparatus to improve individual or selective group of computation tasks such as document compression and decompression algorithms, and bandwidth
operability for selective communications networks. However, cost performance for document database and processing applications can be dramatically improved, provided systems have internal ability to retain the initial document request and subject of
interest, then accurately search through all possible reference resources and analyze and identify the most suitable target material, finally authorize specific procedural and/or instruction steps for each document request.
As a result, the methodology for DISC 112 becomes intrinsically different. RISC or CISC's primary focus are to optimize run-time computation performance, i.e., instruction authorization, decoding, pipelining, arithmetic and logical execution,
and memory control and management. DISC 112 requires and provides additional real time performance for query, reasoning, compilation, decoding, and interpretation of the incoming data streams prior to any instruction authorization or document execution. Comparatively, the RISC and CISC can offer superior performance for numerical intensive data computation applications, wherein DISC 112 is specifically optimized for document retrieval and subsequent procedural authorizations.
Furthermore, prior arts in CISC and RISC only rely on traditional OCR (optical character recognition) techniques to compute, analyze, and recognize characters strings according to individual shapes and contours, whereby DISC 112 allows for 100%
recognition for incoming document data through front-end data decoding subsystem and techniques. As a result, the incoming data streams are decoded to selective internal DISC 112 optimized data format, which including but not limit to the 8 or 16 bit
universal character encoding forms.
Finally, DISC 112 focus on performance optimization other than the traditional RISC/CISC run-time data computation, DISC 112 subsystems include but not limit to, document identification, manipulation, compilation, encoding and decoding,
interpretation, storage and retrieval. Subsequently, all DISC 112 instruction groups are issued and executed to facilitate run-time document manipulation, and to conform specific application, networking, and user priority requests.
The diagrammatic representation illustrated in FIG. 2A comprises the following major system components. They are a personal database (PDB 226), a packet processor (PACK 228) a transmission processor (TX 222), a receiving processor (RX 220), a
decoding processor (DEC 206), a encoding processor (ENC 208), a formatting processor (FORM 210), a smart memory (SMART 212), a reference processor (REF 216), a evaluation processor (EVAL 214), a preprocessor (PREP), a postprocessor (POST), a bandwidth
controller (BAND 228), and a system controller (CON 230).
A. Personal Database (PDB)
In a preferred embodiment, the PDB 226 (personal database) integrated circuit is able to provide an optimized memory storage and management subsystem in order to accumulate, manipulate, store, and retrieve a single or plurality quantities of
personal knowledge content corresponding to the selective DISC 112 internal data format signal it receives from PACK 218 (packet processor).
The PDB 226 integrated circuit is comprised of a single or plurality of storage array that is comprised of a single or plurality of memory storage cells. The PDB 226 is also comprised of the sensing, control, management, and interface circuits
connected locally and/or remotely to a single or plurality of said storage array which transceive, store, and manipulate single or plurality quantities of said personal knowledge content that is comprised of compound document objects corresponding to
said selective DISC 112 internally optimized data format signal. There is also a computation circuit which, when activated, produces logical pointer signal, storage address signal, and/or attribute identifier signal for incoming and/or outgoing said
personal knowledge content. The PDB 226 is further comprised of the buffer, register, and/or stack elements which can store and select said logical pointer, storage address and/or attribute identifier signal to manipulate, prioritize, and retrieve
selective said incoming and/or outgoing personal knowledge content. In addition, The PDB 226 is further comprised of the buffer, control, and interface circuit connected locally and/or remotely to a single or plurality of PACK 218 (packet processor)
integrated circuit which transceive said personal knowledge content that is comprised of selective said logical pointer, storage address signal, attribute identifier signal, compound document object, and/or corresponding DISC 112 internal data format
signal.
In a more preferred embodiment, as shown in FIG. 2B, the PDB 226 (personal database) integrated circuit connected to the OIF 224 (object interface) integrated circuit is further comprised of buffer, control and interface circuits which segregate,
partition, and assign individual knowledge content to single or plurality of personal application environments. There is also buffer, control and management circuits which receive and update input request signal, run-time attribute signal, and/or
priority signal either locally or remotely from a single or plurality of application, user, and/or communications network.
B. Packet Processor (PACK)
in a preferred embodiment, the PACK 218 (packet processor) integrated circuit is able to transcode and interpret DISC 112 compound document control signals corresponding to selective standard or proprietary protocols for communications, operating
systems, text description, database access and/or database management. PACK 218 can also store, relay, translate DISC 112 compound document data signal into single or plurality of frames, packets, cells, or macroblocks corresponding to said standard or
proprietary protocols for inbound or outbound communications. Preferably, the PACK 218 is further able to either locally or remotely communicate with external PACK 218's and to perform point-to-point and point-to-multipoint networking sessions, and to
interpret and control single or plurality layered signalling data structure.
The PACK 218 is comprised of a single or plurality of protocol controller and data processor connected to the ENC 208 (encoding processor) and TX 222 (transmission processor) integrated circuit which receive an encoded DISC 112 control and data
signals from ENC 208 and produce outbound data, control, and maintenance packets, frames, cells, or alike to TX 222 corresponding to selective standard or proprietary protocols for communications, operating systems, text description, database access, and
database management which, when activated, including but not limit to, PDL, SQL, Netware, NT, OS2, DOS, UNIX, Q.931, X.25, G3, G4, GSM, CIF, QCIF, SIF, ATM (asynchronous transmission mode) or alike. Said protocol controller and data processor also
connected to the DEC 206 (decoding processor) and RX 220 (receiving processor) integrated circuits which receives inbound packet, frames, cells, or macroblocks from RX 220 corresponding to said selective protocols and produce DISC 112 control and data
signals to DEC 206 for decoding. There is also a buffer element connected to the TX 222 and RX 220 which transmit and receive document control, maintenance, and data packet, frames, or cells. The PACK 218 is further comprised of a interface, buffer and
control circuits connected to FORM 210 and PDB 226 integrated circuit which, when activated, receive DISC 112 internal reformatted document signals from FORM 210 and enable said buffer circuit to transfer and store said reformatted signal into PDB 226.
Reversely, said pipeline buffer element further retrieve the internally formatted DISC 112 signal from PDB 226 and translate to said selective protocol formatted packets, cells, frames, or macroblocks for outbound communication.
in a more preferred embodiment, said protocol controller is further comprised of controller element connected via TX 222 and RX 220 to a single or plurality of local or remote external PACK's which establish, maintain, and terminate
point-to-point and point-to-multipoint distributed networking sessions, said controller is further comprised of buffer, control and management circuits connected to OIF 224 integrated circuit, as shown in FIG. 2B, which compute input request signal,
run-time attribute signal, and/or priority signal either locally or remotely for a single or plurality of application, user, and/or communications network.
in a further preferred embodiment, said protocol control processor element is comprised of a signalling control circuit which transceive a single or plurality of layered signalling data structure corresponding to selective OSI, SS7, TC/PIP or
alike, and receives, interpret, or produces a single or plurality of user preference signal, application requirement signal, session control signal, transmission set-up signal, network control signal, logical or physical link setup and termination
signal, and/or the alike and translate said signals into corresponding sequence of internal DISC 112 executable procedures or routines.
C. Transmission (TX) and Receiving (RX) Processor
In a preferred embodiment, the TX 222 (transmission processor) and RX 220 (receiving processor) integrated circuit are able to transceive document signal corresponding to a single or plurality of application requirements, networking environments,
user priority requests, and run-time bandwidth conditions.
The TX 222 and RX 220 are comprised of a single or plurality pairs of transceivers which, when activated, correspond to a plurality of analog or digital networks which, including but not limited to: ATM, SONET, broadband ISDN, FDDI, MAN, DS3,
twisted-pair LAN., coaxial LAN, switch T1, dedicated T1, primary rate ISDN, fractional T1, frame relay, ISDN switched H1, single or dual channel basic rate ISDN, digital switched or private PSDN, analog twist-pair, basic rate ISDN D channel, and wireless
communications. The TX 222 and RX 220 are also comprised of sensitizing circuit connected to the PACK 218 integrated circuit which sensitizes run-time networking conditions and produce selective run-time bandwidth allowance signal which, correspond but
not limited to: 150 Mbs, 100 Mbs, 45 Mbs, 10 Mbs, 2.048 Mbs, 1.544 Mbs, 384 Mbs, 128 Mbs, 64 Kbs, Px 64 Kbs, 56 Kbs, 19.2 Kbs, and/or 9.6 Kbs.
In a more preferred embodiment, the TX 222 and RX 220 are further comprised of interface and transceiver circuit connected to the OIF 224 via PACK 218 which transmit and receives input request signal, run-time attribute signal, and/or priority
signal either locally or remotely for a single or plurality of applications, users, and/or communications network.
D. Decoding (DEC) and Encoding (ENC) Processor
In a preferred embodiment, the ENC 208 (encoding processor) and the DEC 206 (decoding processor) integrated circuit are able to locally and/or remotely encode and decode the compiled high level language procedural modules corresponding to a
single or plurality of selective procedural coding algorithms for direct interpretation, execution and manipulation of the source document content. The DEC 206 and the ENC 208 integrated circuit are also able to locally and/or remotely decode DISC 112
data tokens and encode DISC 112 data signal respectively corresponding to a single or plurality of selective compound document data coding algorithms. Preferably, said DEC 206 and ENC 208 can also select said data and/or procedural coding algorithm
employing appropriate mechanisms to meet system performance. More preferably, said DEC 206 and ENC 208 are further able to internally or externally communicate, interface, and perform with single or plurality of software or hardware coprocessor modules.
The DEC 206 is comprised of a single or plurality of time, pel, and/or frequency domain data decoding circuits connected to PREP 202 and PACK 218 which, when activated, receive local or remote encoded tokens and/or bit-map corresponding to a
single or plurality of selective text processor, printer 154, graphic display, fax 110, scanner 158, or copier 156 data format, and convert, transform, and produce source document signal corresponding to selective DISC 112 internal data format. Said DEC
206's data decoding circuits is also comprised of interface, control, and buffer circuit connected to FORM 210 which, when activated, transfer to FORM 210 said source document corresponding to selective DISC 112 internal data format for further analysis
and evaluation. The ENC 208 is comprised of a single or plurality of high level language procedural encoding circuits connected to SMART 212 which, when activated, receive high level language procedures corresponding to selective source document from
SMART 212 and produce direct executable DISC 112 encoded procedures corresponding to single or plurality of procedural coding algorithms. Said ENC's procedural encoding circuit is also comprised of interface, control, and buffer circuit connected to
PACK 218 and REF 216 and EVAL 214 which, when activated, transfer said direct executable DISC 112 encoded procedures for remote and/or local interpretation, manipulation, and operation of said source document. Said DEC 206 and ENC 208 are further
comprised of pipeline buffer and processing circuit connected to POST 204 and PREP 202 which, when activated, respectively produce and receive compatible output and input signal for single or plurality of computer 108, communications, and entertainment
equipment, which include, but not limit to, copier 156, printer 154, scanner, fax 110 machine, telephone 104, camcorder, CD player, television 106, personal computer 108, and personal communications devices.
In a more preferred embodiment, as shown in FIG. 2B, said ENC's and DEC 206's procedural encoding and decoding circuits are further comprised of application/task queuing circuit connected to SMART 212 and CON 230 integrated circuit which, when
activated, look-ahead fetch and retrieve selective group of precompiled and directly executable procedural to selectively control and manipulate said compound document in a single or plurality of application environment. Said DEC 206 and ENC 208 are
further comprised of a single or plurality of time, pel, and/or frequency domain data decoding and encoding circuits connected to PACK 218 which, when activated, retrieve and produce respective decoded DISC 112 signal and encoded DISC 112 tokens
correspond to a single or plurality of time, pel, and/or frequency domain coding algorithms, and for a single or plurality of compound document data types which, including but not limit to text, ASCII data, audio, image, graphics, and video. Said ENC's
and DEC's procedural and data processing circuits are further comprised of a pipeline buffer circuit connected to SMART 212 and PACK 218, which when activated, either receive encoded tokens from SMART 212 or PACK 218 for decoding, transfer decoded or
encoded signals and procedures | | |
