A self-aligned via structure and its method of manufacture comprising the steps of providing a semiconductor substrate, and then sequentially forming a conductive layer and a dielectric layer over the substrate. Next, a hollow cavity is etched out in the dielectric layer. Then, a photolithographic process is performed by coating a photoresist layer over the dielectric layer and the cavity, followed by creating a pattern of desired conductive lines so that portions of the photoresist layer overlaps with the cavity. Subsequently, using the photoresist layer as a mask, the dielectric layer and the conductive layer are etched to form a multiple of conductive lines. Thereafter, a selective liquid phase deposition is performed to deposit an oxide layer over the substrate in regions outside the photoresist-occupied regions. Finally, the photoresist layer is removed to form the via structure of this invention in the oxide layer.
A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.
A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.
