Method and apparatus for hiding data path equilibration time

Claims

We claim:

1. A data path for use in a memory device to couple a differential data signal from a first pair of complementary data nodes to a second pair of complementary data nodes, the data path comprising:

a first coupling device having a complementary pair of input terminals coupled to the first pair of complementary data nodes, the first coupling device having first and second complementary pairs of output terminals;

a second coupling device having first and second complementary pairs of input terminals and a complementary pair of output terminals coupled to the second pair of complementary data nodes;

a first complementary data path electrically coupled between the first output terminals of the first coupling device and the first input terminal of the second coupling device;

a second complementary data path electrically coupled between the second output terminals of the first coupling device and the second input terminal of the second coupling device; and

at least one equilibration circuit selectively coupled to the first and second data paths.

2. The data path of claim 1 wherein the first and second complementary data paths comprise complementary I/O lines electrically coupled between a plurality of digit lines and a complementary pair of data lines.

3. The data path of claim 1 wherein the first and second complementary data paths comprise complementary data lines electrically coupled between a complementary pair of I/O lines and a DC sense amplifier.

4. The data path of claim 1 wherein the first and second complementary data paths comprise complementary I/O lines and data lines electrically coupled in series between a plurality of digit lines and a DC sense amplifier.

5. The data path of claim 1 wherein the first and second complementary data paths comprise complementary I/O lines, data lines, a DC sense amplifier, and complementary read data lines electrically coupled in series between a plurality of digit lines and a data output buffer.

6. The data path of claim 1 wherein the first and second complementary data paths comprise a DC sense amplifier, and complementary read data lines electrically coupled in series between a complementary pair of data lines and a data output buffer.

7. The data path of claim 1 wherein the first and second complementary data paths comprise a write driver circuit and a complementary pair of data write lines electrically coupled in series between an input buffer and complementary pair of data lines.

8. The data path of claim 1 wherein each of the first and second complementary data paths is coupled to at least one equilibration circuit to alternatively equilibrate the respective data paths.

9. A data path adapted for use in a memory device having a memory cell array, a pair of digit lines providing memory cell data from the memory cell array, and a sense amplifier producing a differential signal based on the memory cell data, the data path comprising:

an I/O line select circuit having a complementary pair of input terminals coupled to receive the differential signal from the sense amplifier and first and second complementary pairs of output terminals coupled to provide the differential signal, the I/O line select circuit alternatively selecting from the first and second pairs of output terminals to provide the differential signal;

first and second complementary pairs of I/O lines coupled to the first and second pairs of output terminals of the I/O select circuit, respectively, to transmit the differential signal;

a data line pass gate circuit having first and second complementary pairs of input terminals coupled to the first and second pair of I/O lines, respectively, and a complementary pair of output terminals, the pass gate circuit alternatively selecting from the first and second pairs of I/O lines to provide the differential signal to the complementary pair of output terminals; and

first and second equilibration circuits electrically coupled to the first and second complementary pair of I/O lines, respectively, between the I/O line select circuit and the pass gate circuit, the equilibration circuits establishing a common and predetermined voltage on the respective complementary pair of I/O lines when the respective I/O lines is not selected by the data line pass gate circuit.

10. The data path of claim 9, further comprising:

a DC sense amplifier having a complementary pair of input terminals coupled to the complementary pair of output terminals of the data line pass gate and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified differential signal at the pair of output terminals based on the differential signal received from the pass gate circuit;

a first data read line pass gate circuit having a complementary pair of input terminals coupled to the complementary pair of output terminals of the DC sense amplifier to receive the amplified signal and first and second complementary pairs of output terminals, the first data read line pass gate circuit alternatively selecting between the first and second pair of output terminals to be coupled to the input terminals and provide the amplified differential signal;

a first and second complementary pair of data read lines coupled to the first and second pairs of output terminals of the first data read line pass gate, respectively, to transmit the amplified differential signal;

a second data read line pass gate having first and second complementary pairs of input terminals coupled to the first and second pair of data read lines, respectively, and a complementary pair of output terminals, the second data read line pass gate circuit coupling the data read line selected by the first data read line pass gate circuit to the complementary pair of output terminals to provide the amplified differential signal; and

third and fourth equilibration circuits coupled to the first and second complementary pair of data read lines, respectively, between the first and second data read line pass gate circuits, the equilibration circuits establishing a common and predetermined voltage on the respective complementary pair of data read lines when the respective data read line is not selected by the first and second data read line pass gate circuits.

11. The data path as in claim 10, further comprising a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the second data read line pass gate circuit to receive the amplified differential signal, the data output circuit being structured to generate a data signal at a data output terminal based on the amplified signal.

12. The data path of claim 10 wherein the third and fourth equilibration circuits comprise:

a first switch having signal terminals coupled between the complementary pair of data read lines, and a control terminal, the first switch electrically coupling the pair of data read lines when the first switch is turned on; and

a pair of switches series connected and coupled between the complementary pair of data read lines, and having an intermediate node between the switches coupled to a predetermined reference voltage and a pair of control terminals coupled together and to the control terminal of the first switch, the pair of switches providing the predetermined reference voltage to the pair of data read lines when the pair of switches is turned on.

13. The data path of claim 9 wherein the first and second equilibration circuits comprise:

a first switch having signal terminals coupled between the complementary pair of I/O lines, and a control terminal, the first switch electrically coupling the pair of I/O lines when the first switch is turned on; and

a pair of switches series connected and coupled between the complementary pair of I/O lines, and having an intermediate node between the switches coupled to a predetermined reference voltage and a pair of control terminals coupled together and to the control terminal of the first switch, the pair of switches providing the predetermined reference voltage to the pair of I/O lines when the pair of switches is turned on.

14. A data path adapted for use in a memory device having a memory cell array, a pair of digit lines providing memory cell data from the memory cell array, and a sense amplifier producing a differential signal based on the memory cell data, the data path comprising:

an I/O line select circuit having a complementary pair of input terminals coupled to the sense amplifier and first and second complementary pairs of output terminals coupled to provide the differential signal, the I/O line select circuit alternatively selecting from the first and second pairs of output terminals to provide the differential signal;

first and second complementary pairs of I/O lines coupled to the first and second pairs of output terminals of the I/O select circuit, respectively, to transmit the differential signal;

a data line pass gate circuit having first and second complementary pairs of input terminals coupled to the first and second pair of I/O lines, respectively, and a complementary pair of output terminals, the pass gate circuit alternatively selecting between the first and second pairs of I/O lines to couple to the complementary pair of output terminals to transmit the differential signal;

a first equilibration circuit electrically coupled to the first complementary pair of I/O lines between the I/O line select circuit and the pass gate circuit, the first equilibration circuit establishing a predetermined voltage on the first complementary pair of I/O lines when not selected by the pass gate circuit;

a second equilibration circuit electrically coupled to the second complementary pair of I/O lines between the I/O line select circuit and the pass gate circuit, the second equilibration circuit establishing a predetermined voltage on the second complementary pair of I/O lines when not selected by the pass gate circuit; and

a DC sense amplifier having a complementary pair of input terminals coupled to the complementary pair of output terminals of the pass gate and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified signal at the complementary pair of output terminals based on the differential signal received from the pass gate circuit.

15. A data path as in claim 14, further comprising:

a first data read line pass gate circuit having a complementary pair of input terminals coupled to the complementary pair of output terminals of the DC sense amplifier to receive the amplified signal and first and second complementary pairs of output terminals, the first data read line pass gate circuit alternatively selecting from the first and second pair of output terminals to be coupled to the input terminals and provide the amplified signal;

a first and second complementary pair of data read lines coupled to the first and second pairs of output terminals of the first day to read line past gate, respectively;

a second data read line pass gate having first and second complementary pairs of input terminals coupled to the first and second pair of data read lines, respectively, and a complementary pair of output terminals, the second data read line pass gate circuit coupling the data read line selected by the first data read line to the complementary pair of output terminals to provide the amplified signal;

a third equilibration circuit electrically coupled to the first complementary pair of data read lines between the first and second data read line pass gate circuits, the third equilibration circuit establishing a predetermined voltage on the first complementary pair of data read lines when not coupled by the first and second data read line pass gate circuits;

a fourth equilibration circuit electrically coupled to the second complementary pair of data read lines between the first and second data read line pass gate circuits, the fourth equilibration circuit establishing a predetermined voltage on the second complementary pair of data read lines when not coupled by the first and second data read line pass gate circuits; and

a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the second data read line pass gate circuit to receive the amplified signal, the data output circuit being structured to generate a data signal at a data output terminal based on the amplified signal.

16. A memory device comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a complementary pair of digit lines;

a sense amplifier for each column, each sense amplifier having a pair of terminals coupled respectively to the digit lines of a respective one of the columns, the sense amplifier being structured to amplify a differential data signal on the digit lines;

a data path for coupling the differential data signal from a first pair of complementary data nodes to a second pair of complementary data nodes, the data path comprising:

a first multiplexer having a complementary pair of input terminals coupled to the first pair of complementary data nodes, the first multiplexer having first and second complementary pairs of output terminals;

a second multiplexer having first and second complementary pairs of input terminals and a complementary pair of output terminals coupled to the second pair of complementary data nodes;

a first complementary data path coupled between the first output terminals of the first multiplexer and the first input terminal of the second multiplexer;

a second complementary data path coupled between the second output terminals of the first multiplexer and the second input terminal of the second multiplexer;

at least one equilibration circuit capable of coupling to the first and second data paths;

a DC sense amplifier having a complementary pair of inputs coupled to the data path to receive the differential data signal and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified differential signal at the pair of output terminals based on the differential data signal received from the data path; and

a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the DC sense amplifier to receive the amplified differential signal, the data output circuit being structured to provide a data signal to the data output terminal based on the amplified differential signal.

17. The memory device of claim 16 wherein the first and second complementary data paths comprise I/O lines electrically coupled between a plurality of digit lines and a complementary pair of data lines.

18. The memory device of claim 16 wherein the first and second complementary data paths comprise data lines electrically coupled between a complementary pair of I/O lines and a DC sense amplifier.

19. The memory device of claim 16 wherein the first and second complementary data paths comprise I/O lines and data lines electrically coupled in series between a plurality of digit lines and a DC sense amplifier.

20. The data path of claim 16 wherein the first and second complementary data paths comprise I/O lines, data lines, a DC sense amplifier, and read data lines electrically coupled in series between a plurality of digit lines and a data output buffer.

21. The memory device of claim 16 wherein the first and second complementary data paths comprise a DC sense amplifier, and read data lines electrically coupled in series between a complementary pair of data lines and a data output buffer.

22. The memory device of claim 16 wherein the first and second complementary data paths comprise a write driver circuit and a complementary pair of data write lines electrically coupled in series between an input buffer and complementary pair of data lines.

23. The memory device of claim 16 wherein the first and second complementary data paths have at least one equilibration circuit to alternatively equilibrate the respective data paths.

24. A memory device comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a complementary pair of digit lines;

a sense amplifier for each column, each sense amplifier having a pair of terminals coupled respectively to the digit lines of a respective one of the columns, the sense amplifier being structured to amplify a differential data signal on the digit lines;

a data path being coupled to a selected one of the pairs of digit lines to receive the differential data signal from the selected digit lines, the data path comprising:

an I/O line select circuit having a complementary pair of input terminals receiving the differential signal, and first and second complementary output terminals, the I/O line select circuit alternatively selecting from the first and second pairs of output terminals to provide the differential signal;

first and second complementary pairs of I/O lines coupled to the first and second pairs of output terminals of the I/O select circuit, respectively, to transmit the differential signal;

a data line pass gate circuit having first and second complementary pairs of input terminals coupled to the first and second pair of I/O lines, respectively, and a complementary pair of output terminals, the pass gate circuit alternatively selecting from the first and second pairs of I/O lines to provide the differential signal to the complementary pair of output terminals; and

first and second equilibration circuits electrically coupled to the first and second complementary pair of I/O lines, respectively, between the I/O line select circuit and the data line pass gate circuit, the equilibration circuits establishing a common and predetermined voltage on the respective complementary pair of I/O lines when the respective I/O lines is not selected by the data line pass gate circuit;

a DC sense amplifier having a complementary pair of inputs coupled to the data path to receive the differential data signal and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified differential signal at the pair of output terminals based on the differential data signal received from the data path; and

a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the DC sense amplifier to receive the amplified differential signal, the data output circuit being structured to provide a data signal to the data output terminal based on the amplified differential signal.

25. The memory device of claim 24, further comprising:

a first data read line pass gate circuit having a complementary pair of input terminals coupled to the complementary pair of output terminals of the DC sense amplifier to receive the amplified signal and first and second complementary pairs of output terminals, the first data read line pass gate circuit alternatively selecting from the first and second pair of output terminals to be coupled to the input terminals and provide the amplified signal;

a first and second complementary pair of data read lines coupled to the first and second pairs of output terminals of the first data read line pass gate, respectively;

a second data read line pass gate having first and second complementary pairs of input terminals coupled to the first and second pair of data read lines, respectively, and a complementary pair of output terminals coupled to the data output circuit, the second data read line pass gate circuit coupling the data read line selected by the first data read line pass gate circuit to the complementary pair of output terminals to provide the amplified signal; and

third and fourth equilibration circuits electrically coupled to the first and second complementary pair of data read lines, respectively, between the first and second data read line pass gate circuits, the equilibration circuits establishing a predetermined voltage on the respective complementary pair of data read lines when the respective data read line is not selected by the first and second data read line pass gate circuits.

26. A computer system comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a complementary pair of digit lines;

a sense amplifier for each column, each sense amplifier having a pair of terminals coupled respectively to the digit lines of a respective one of the columns, the sense amplifier being structured to amplify a differential data signal on the digit lines;

a data path for coupling the differential data signal from a first pair of complementary data nodes to a second pair of complementary data nodes, the data path comprising:

a first multiplexer having a complementary pair of input terminals coupled to the first pair of complementary data nodes, the first multiplexer having first and second complementary pairs of output terminals;

a second multiplexer having first and second complementary pairs of input terminals and a complementary pair of output terminals coupled to the second pair of complementary data nodes;

a first complementary data path electrically coupled between the first output terminals of the first multiplexer and the first input terminal of the second multiplexer;

a second complementary data path electrically coupled between the second output terminals of the first multiplexer and the second input terminal of the second multiplexer;

at least one equilibration circuit capable of coupling to the first and second data paths;

a DC sense amplifier having a complementary pair of inputs coupled to the data path to receive the differential data signal and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified differential signal at the pair of output terminals based on the differential data signal received from the data path; and

a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the DC sense amplifier to receive the amplified differential signal, the data output circuit being structured to provide a data signal to the data output terminal based on the amplified differential signal.

27. The computer system of claim 26 wherein the first and second complementary data paths comprise I/O lines electrically coupled between a plurality of digit lines and a complementary pair of data lines.

28. The computer system of claim 26 wherein the first and second complementary data paths comprise data lines electrically coupled between a complementary pair of I/O lines and a DC sense amplifier.

29. The computer system of claim 26 wherein the first and second complementary data paths comprise I/O lines and data lines electrically coupled in series between a plurality of digit lines and a DC sense amplifier.

30. The computer system of claim 26 wherein the first and second complementary data paths comprise I/O lines, data lines, a DC sense amplifier, and read data lines electrically coupled in series between a plurality of digit lines and a data output buffer.

31. The computer system of claim 26 wherein the first and second complementary data paths comprise a DC sense amplifier, and read data lines electrically coupled in series between a complementary pair of data lines and a data output buffer.

32. The computer system of claim 26 wherein the first and second complementary data paths comprise a write driver circuit and a complementary pair of data write lines electrically coupled in series between an input buffer and complementary pair of data lines.

33. The computer system of claim 26 wherein the first and second complementary data paths have at least one equilibration circuit to alternatively equilibrate the respective data paths.

34. A computer system comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising:

at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a complementary pair of digit lines;

a sense amplifier for each column, each sense amplifier having a pair of terminals coupled respectively to the digit lines of a respective one of the columns, the sense amplifier being structured to amplify a differential data signal on the digit lines;

a data path being coupled to a selected one of the pairs of digit lines to receive the differential data signal from the selected digit lines, the data path comprising:

an I/O line select circuit having a complementary pair of input terminals receiving the differential signal, and first and second complementary output terminals, the I/O line select circuit alternatively selecting from the first and second pairs of output terminals to provide the differential signal;

first and second complementary pairs of I/O lines coupled to the first and second pairs of output terminals of the I/O select circuit, respectively, to transmit the differential signal;

a data line pass gate circuit having first and second complementary pairs of input terminals coupled to the first and second pair of I/O lines, respectively, and a complementary pair of output terminals, the pass gate circuit alternatively selecting from the first and second pairs of I/O lines to couple to the complementary pair of output terminals to transmit the differential signal; and

first and second equilibration circuits electrically coupled to the first and second complementary pair of I/O lines, respectively, between the I/O line select circuit and the data line pass gate circuit, the equilibration circuits establishing a predetermined voltage on the respective complementary pair of I/O lines when the respective I/O lines is not selected by the data line pass gate circuit;

a DC sense amplifier having a complementary pair of inputs coupled to the data path to receive the differential data signal and a complementary pair of output terminals, the DC sense amplifier being structured to generate an amplified differential signal at the pair of output terminals based on the differential data signal received from the data path; and

a data output circuit having a complementary pair of input terminals coupled to the pair of output terminals of the DC sense amplifier to receive the amplified differential signal, the data output circuit being structured to provide a data signal to the data output terminal based on the amplified differential signal.

35. The computer system of claim 34 wherein the memory device further comprises:

a first data read line pass gate circuit having a complementary pair of input terminals coupled to the complementary pair of output terminals of the DC sense amplifier to receive the amplified signal and first and second complementary pairs of output terminals, the first data read line pass gate circuit alternatively selecting between the first and second pair of output terminals to be coupled to the input terminals and provide the amplified signal;

a first and second complementary pair of data read lines coupled to the first and second pairs of output terminals of the first data read line pass gate, respectively;

a second data read line pass gate having first and second complementary pairs of input terminals coupled to the first and second pair of data read lines, respectively, and a complementary pair of output terminals coupled to the data output circuit, the second data read line pass gate circuit coupling the data read line selected by the first data read line pass gate circuit to the complementary pair of output terminals to provide the amplified signal; and

third and fourth equilibration circuits coupled to the first and second complementary pair of data read lines, respectively, between the first and second data read line pass gate circuits, the equilibration circuits establishing a predetermined voltage on the respective complementary pair of data read lines when the respective data read line is not selected by the first and second data read line pass gate circuits.

36. A method of coupling differential data in a memory device from a first pair of complementary data nodes to a second pair of complementary data nodes, the method comprising:

selecting alternatively from first and second complementary data paths, each electrically coupled between the first and second pairs of complementary data nodes, a selected data path to couple the differential data from the first pair of complementary data nodes to the second pair of complementary data nodes and an unselected data path to be electrically isolated from the first and second complementary data nodes; and

equilibrating the unselected data path.

37. The method of claim 36 wherein selecting alternatively comprises selecting from first and second complementary I/O lines electrically coupled between a plurality of digit lines and a complementary pair of data lines.

38. The method of claim 36 wherein selecting alternatively comprises selecting from first and second complementary data lines electrically coupled between a complementary pair of I/O lines and a DC sense amplifier.

39. The method of claim 36 wherein selecting alternatively comprises selecting from first and second complementary I/O lines and data lines electrically coupled in series between a plurality of digit lines and a DC sense amplifier.

40. The method of claim 36 wherein selecting alternatively comprises selecting from first and second complementary I/O lines, data lines, a DC sense amplifier, and complementary read data lines electrically coupled in series between a plurality of digit lines and a data output buffer.

41. The method of claim 36 wherein selecting alternatively comprises selecting from first and second DC sense amplifiers, and complementary read data lines electrically coupled in series between a complementary pair of data lines and a data output buffer.

42. The method of claim 36 wherein selecting alternatively comprises selecting from first and second write driver circuits and complementary pair of data write lines electrically coupled in series between an input buffer and complementary pair of data lines.

43. A method of coupling differential data in a memory device from a first pair of complementary data nodes to a second pair of complementary data nodes, the method comprising:

selecting alternatively from first and second complementary data paths, each extending between the first and second pairs of complementary data nodes, a selected data path to couple the differential data from the first pair of complementary data nodes to the second pair of complementary data nodes and an unselected data path to be electrically isolated from the first and second complementary data nodes; and

equilibrating the unselected data path by using at least one equilibration circuit to alternatively equilibrate the respective data paths.

44. A method of coupling a data signal to a data output circuit of a memory device having a memory cell array arranged in rows and columns, a pair of digit lines providing memory cell data from the memory cell array, and a sense amplifier producing a differential signal based on the memory cell data, the method comprising:

selecting alternatively between a first and second complementary pair of I/O lines to receive and transmit the differential signal;

equilibrating the complementary pair of I/O lines not selected;

coupling the selected complementary pair of I/O lines to a DC sense amplifier to produce at its output an amplified differential signal based on the differential signal; and

coupling the output of the DC sense amp to the data output circuitry.

45. The method of claim 44 wherein coupling the output of the DC sense amp to the data output circuitry comprises:

selecting alternatively between a first and second complementary pair of data read lines to receive and transmit the data signal from the DC sense amplifier;

equilibrating the complementary pair of data read lines not selected; and

coupling the selected complementary pair of data read lines to the data output circuitry.

46. A method of coupling a data signal to a data output circuit of a memory device having a memory cell array arranged in rows and columns, a pair of digit lines providing memory cell data from the memory cell array, and a sense amplifier producing a differential signal based on the memory cell data, the method comprising:

selecting alternatively between a first and second complementary pair of I/O lines to receive and transmit the differential signal;

equilibrating the complementary pair of I/O lines not selected,

coupling the selected complementary pair of I/O lines to a DC sense amplifier to produce at its output an amplified differential signal based on the differential signal; and

coupling the output of the DC sense amp to the data output circuitry, wherein the coupling comprises:

selecting alternatively between the first and second complementary pair of data read lines to receive and transmit the data signal from the DC sense amplifier by selecting the first pair of data read lines when the first complementary pair of I/O lines is selected, and selecting the second pair of data read lines when the second pair of I/O lines is selected;

equilibrating the complementary pair of data read lines not selected; and

coupling the selected complementary pair of data read lines to the data output circuitry.

47. The method of claim 44 wherein equilibrating the complementary pair of I/O lines comprises:

coupling the complementary pair of I/O lines together to equalize an electrical potential on each I/O line; and

coupling the complementary pair of I/O lines to a predetermined reference voltage to precondition the electrical potential on each I/O line.

48. A method of coupling a differential data signal from a data input circuit of the memory device having a memory cell array arranged in rows and columns, and a pair of digit lines providing the differential data signal to the memory cell array, the method comprising:

selecting alternatively between a first and second complementary pair of data write lines to couple to and transmit the differential data signal from the data input circuit to a write driver circuit;

equilibrating the complementary pair of data write lines not selected;

coupling the selected complementary pair of data write lines to the write driver circuit to write the differential data signal to the memory cell array; and

coupling the output of the write driver circuit to the pair of digit lines to transmit the differential data signal to the memory cell array.

49. The method of claim 48 wherein coupling the output of the write driver circuit to the pair of digit lines comprises:

selecting alternatively between a first and second complementary pair of I/O lines to couple to and transmit the differential signal from the write driver circuit;

equilibrating the complementary pair of I/O lines not selected; and

coupling the selected complementary pair of I/O lines to the write diver circuit and the pair of digit lines.

TECHNICAL FIELD

The invention relates generally to integrated circuit memory devices, and more particularly, to a data path in a memory device.

BACKGROUND OF THE INVENTION

As the processing speed of microprocessors increases, the demand for memory devices having faster access times also increases. Memory system designers have developed methods and designs that shave off nanoseconds from access times in order to satisfy the demand for high speed memory devices. Such designs have included memory devices having various data access modes, for example, devices that have a burst mode or page mode. Memory system designers have more recently developed synchronous memory systems that allow the pipelined transfer of data at the clock speed of the motherboard. Currently, there has been a movement toward memory designs that can transfer data at clock speeds optimized for the particular memory configuration. However, even with the advances made in memory system designs, the fundamental building blocks of memory devices have remained relatively the same. As will be described in more detail below, these building blocks are the basic elements that are shared among all types of memory devices, regardless of whether they are synchronous or asynchronous, random-access or read-only, or static or dynamic.

A conventional memory device is illustrated in FIG. 1. The memory device includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address.

After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. The column address latch 40 momentarily stores the column address while it is provided to the column address buffer 44. The column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers and associated column circuits 50 and 52 for the respective arrays 20 and 22.

Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50 or 52, respectively, and a read data path that includes a data output register 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input register 60, to one of the column circuits 50 or 52 where they are transferred to one of the arrays 20 or 22, respectively.

The above-described operation of the memory device 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the "*" designates the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.

As mentioned above, read data are coupled from one of the arrays 20 and 22 to the data bus 58 through a read data path that is shown in greater detail in FIG. 2. The read data path 80 begins in one of the columns in the array 20 (FIG. 1). The column includes a complementary pair of digit lines 84 and 86 coupled to the memory cells in the column. A sense amplifier 88 connected between the digit lines 84 and 86 amplifies a differential data signal 10 on the digit lines 84 and 86 in a well-known manner. The differential data signal indicates the presence of a "1" or a "0" in an enabled memory cell in the column.

The digit lines 84 and 86 are selectively coupled to a complementary pair of I/O lines 90 and 92 through a column switch 89 when the column select signal CSEL0 goes high. Prior to coupling to the digit lines 84, 86, the I/O lines 90, 92 are equilibrated and biased to a predetermined reference voltage level by an equilibration circuit 93. The equilibration circuit 93 ensures that the voltage levels of the I/O lines 90, 92 are approximately equal and at a predetermined reference voltage level so that the differential data signal on the digit lines 84, 86 will be accurately coupled to the I/O lines 90, 92. The equilibration circuit 93 is activated when the equilibration signal EQ goes high. The I/O lines 90 and 92 are also selectively coupled to the digit lines for a large number of other columns, but these other digit lines have been omitted from FIG. 2 for purposes of clarity. The I/O lines 90, 92 must be equilibrated every time the I/O lines 90, 92 are to be coupled to another pair of digit lines.

The I/O lines 90 and 92 are selectively coupled to a complementary pair of data lines 94 and 96 by first and second pass gates 98 and 100. Another pair of I/O lines 194, 196 is also shown coupling to the data lines 94, 96 to represent the fact that the data lines 94, 96 may be selectively coupled to at least one other complementary pair of I/O lines through a multiplexer, which is represented by the pass gates 98, 100, 198, 199. The use of a multiplexer allows the data lines 94, 96 to be shared with several other pairs of I/O lines. A conductive state of each of the pass gates 98 and 100 determines which pair of I/O lines is to be coupled to the data lines 94, 96, and is controlled by a complementary select signals SEL, SEL* derived from the column address. When the pass gates 98 and 100 are rendered conductive, the differential data signal is coupled from the digit lines 84 and 86 through the I/O lines 90 and 92 to the data lines 94 and 96. As with the I/O lines, the data lines 94, 96 need to be equilibrated prior to coupling to the I/O lines 90, 92. The equilibration circuit 93 is activated before the pass gates 98 and 100 become conductive to bias the data lines 94, 96 to an equal and a predetermined voltage reference level. Immediately prior to coupling to the I/O lines 90, 92, the equilibration 93 circuit is deactivated. However, an equilibration circuit (not shown) separate from the equilibration circuit 93 may be used to equilibrate the data lines 94 and 96.

The data lines 94 and 96 are coupled, respectively, to complementary inputs of a DC sense amplifier 110. The DC sense amplifier 110 is a high speed, high gain differential amplifier that amplifies the differential data signal on the data lines 94 and 96 to full CMOS voltage levels. An amplified differential data signal is generated by the DC sense amplifier 110 at complementary outputs and provided to a complementary pair of data read lines 112 and 114. As with the I/O lines and data lines, the data read lines 112, 114 must also be equilibrated by an equilibration circuit 111 prior to amplification by the DC sense amplifier 110 in order to accurately amplify the differential data signal. The data read lines 112 and 114 provide the amplified differential data signal to a complementary pair of inputs in a data output buffer 126, which provides a data signal to a data bus terminal 128 based on the amplified differential data signal. Although not shown in FIG. 2, the DC sense amplifier 110 may be coupled to at least one other complementary pair of data lines (not shown) through a multiplexer (not shown). Thus, the DC sense amplifier 110 may be shared between more than one pair of complementary data lines, in a manner similar to the coupling between the I/O lines and the data lines 94, 96.

In contrast to the data read sequence previously described, the data write sequence begins when input data is received by an input buffer 150 from the data bus terminal 128. Prior to receiving the input data, data write lines 152, 154 have been equilibrated by equilibration circuit 155. The input buffer 150 generates a differential data signal based on the input data and is coupled to a write driver circuit 158 using the data write lines 152, 154. The complementary output terminals of the write driver 158 are coupled to the data lines 94, 96 and the I/O lines 90, 92. When the column switch 89 couples the I/O lines 90, 92 and data lines 94, 96 to a selected pair of digit lines 84, 86, the write driver 158 writes data from the input buffer 150 to the memory cell array 20 (FIG. 1). As illustrated by this example, several elements of the read data paths and write data paths are shared between the read and write operations. For example, the I/O lines 90, 92 and data lines 94, 96 have bidirectional data capability and can be used for both reading from and writing the memory cell array 20. However, other elements are designed to transmit data in only one direction, and are thus specific to either the read or write operation. For example, data read lines 112, 114 are used only for reading data from the memory cell array. When writing data to the memory cell array, the data write lines 152, 154 are used instead.

A common operation with regard to complementary signal lines is that they all must be equilibrated prior to coupling to a differential data signal in order to accurately provide the differential data signal to the next stage of the data path. The problem with existing complementary data paths is that there may be some delay in coupling a differential data signal because of the time it takes to equilibrate the complementary signal lines. For example, in a memory device such as the one shown in FIG. 1, the equilibration time directly adds to the data transfer time of the memory device. The equilibration delay may affect the complementary signal lines used during a data read operation, as well as during a data write operation. The delay associated with equilibration may not be a problem for the complementary digit lines 84 and 86 because the same pair of digit lines is not generally used for successive data transfers. However, the same pair of I/O lines 90 and 92 and the same pair of data lines 94 and 96 are often used for successive data transfers. Before successive data transfers can occur, the I/O lines 90 and 92 and the data lines 94 and 96 must have been equilibrated. As the demand for memory devices having lower data access times becomes greater, the time lag added by any equilibration time may no longer be acceptable. Therefore, there is a need for a data path that can couple differential data without any delay due to equilibrating the data path.

SUMMARY OF THE INVENTION

A method and apparatus for hiding equilibration time of a differential data path using a first and second complementary pair of signal lines alternatively coupled to provide a differential data signal. One complementary pair of signal lines couples the differential data signal while the uncoupled pair of signal lines is equilibrated in preparation for coupling to a subsequent differential data signal. The first and second complementary pair of signal lines may be I/O lines coupled in parallel between a pair of digit lines from a memory cell array and a DC sense amplifier. The first and second complementary pair of signal lines may alternatively or additionally be data read lines coupled in parallel between the DC sense amplifier and the data output circuit. The method and apparatus may be used for both reading from and writing to the memory cell array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a memory device according to the prior art.

FIG. 2 is a block diagram of a read data path according to the prior art.

FIG. 3 is a block diagram of a hidden read data path according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an equilibration circuit that may be used in the embodiments of the present invention.

FIG. 5 is a block diagram of a hidden read data path according to another embodiment of the present invention.

FIG. 6 is a block diagram of a of a hidden read data path according to another embodiment of the present invention.

FIG. 7 is a block diagram of a memory device including an embodiment of the hidden read data path of FIGS. 3, 5, or 6.

FIG. 8 is a block diagram of a computer system using a plurality of memory devices, each of which includes an embodiment of the hidden read data path of FIGS. 3, 5, or 6.

DETAILED DESCRIPTION OF THE INVENTION

A hidden data path 200 according to one embodiment of the invention is shown in FIG. 3. The hidden data path 200 includes two complementary pairs of I/O lines 216, 218 and 220, 222 connected in parallel between the selected digit lines 204, 206 and the data lines 94, 96. As will be explained below, the two pairs of I/O lines 216, 218 and 220, 222 are alternatively selected to transmit the differential data from the digit lines 204, 206 to the DC sense amplifier 262. In order to